Huawei Technologies Co., Limited

China Iwncomm Co., Ltd.

Jiayin Lu

Yu Liu

Jun Cao

Zhe Li

Bo Wang

Zhenhai Huang

Xiang Li

Xiang Yan

Cong Yao

ZhuFeng Tan

Liqian Chen

Feifei Yin

Shiming He

Qiwei Liu

Jun Huang

Qiang Ding

Kun Peng Wang

Haofeng Wang

Chongliang Ma

Jianbo He

Zhufeng Tan

The present application provides example terminal chips. One example terminal chip includes a security element, an application processor, and an interface module configured to transfer information between the application processor and the security element. The terminal chip includes a first power interface configured to receive power outside the terminal chip. A first power input port of the security element is connected to the first power interface, and at least one of the application processor or the interface module is connected to the first power interface. In the example terminal chip, a power supply port of the security element is connected to a power supply port of the application processor or the interface module of the terminal chip.

Terminal chip integrated with security element

A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

Data protection circuit of chip, chip, and electronic device

A chip, including a selector, a one-time programmable (OTP) device, and a controller, where the controller is separately coupled to a selection end of the selector and the OTP device, and the controller is configured to detect a device value of the OTP device, and provide a first selection signal when the device value of the OTP device is within a first preset range. A first input end of the selector is configured to receive access data, a second input end of the selector is configured to receive a preset invalid value, and an output end of the selector is coupled to the OTP device. The selector is configured to control the data received by the second input end to be output from the output end of the selector when the first selection signal is input.

Chip and chip burning method

The present invention provide a method and a detection circuit for detecting a security chip operating slate. The detection circuit includes: a first register unit, a triggering unit, a delay unit, a routing unit, and a second register unit, where the second register unit is connected to the triggering unit. A first signal is delayed in the delay unit, to obtain a second signal, a third signal is obtained according to the second signal, and logical operation is performed on the first signal and the third signal, to output a level signal to trigger an alarm unit. Because each unit may be implemented by using a digital circuit, a size of the circuit can be reduced.

Method and detection circuit for detecting security chip operating state

The present invention provides a display control method and system, and a display device. The method includes acquiring a status value of a display buffer; comparing the status value of the display buffer with a preset warning value of the display buffer; and adjusting a value of a depth of outstanding bus commands according to a comparison result. In the embodiments of the present invention, a status value of the display buffer is compared with a preset warning value of the display buffer, where the status value of the display buffer reflects a change to a current load; it may be determined whether a status value of the display buffer corresponding to the current load is normal according to a comparison result; and a value of a depth of outstanding bus commands is adjusted accordingly, effectively resolve a data real-timeness issue, and ensure that an entire system efficiently runs.

Display control method and system and display device

An embodiment of the present invention discloses a method for quickly responding to a signal, where the method includes: generating a frame synchronization signal; pre-reading image data, and saving the image data after processing the image data; and receiving a TE signal, and outputting the processed image data according to the TE signal. An embodiment of the present invention further discloses an apparatus for quickly responding to a signal. Using the present invention may improve a rate for responding to a signal and reduce an instantaneous bandwidth pressure on a transmission line.

Method and apparatus for quickly responding to signal

An encryption and decryption processing system for achieving SMS4 cryptographic procedure can be provided. The system includes a repeating encryption and decryption data processing device comprising a first constant array storing unit, a first data registering unit and a first data converting unit. The first constant array storing unit stores a first constant array and send it to N-data converting sub-units of the first data converting unit. The first data registering unit registers data, deliver the registered data to a first data converting sub-unit. The N-data converting sub-units perform a data conversion processing, and transmit the obtained conversion data to a next data converting sub-unit for subsequent processing until the data conversion processing processes are completed, a particular number of the completed processed being equal to a value of a data depth.

Encryption and decryption processing method, system and computer-accessible medium for achieving SMS4 cryptographic procedure

The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.

Circuitry for clock and method for providing clock signal

A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).

Variable-frequency bus adapter, adapting method and system

An encrypting/decrypting processing method for implementing SMS4 algorithm in high efficiency is provided. After preparing constant array, input external data into register section, firstly make primary data conversion and then make secondary data conversion, finally repeat data conversion course until complete all specified data conversion courses and obtain processing result of circulating data encryption/decryption. And it solves the technical problems of data conversion in the background technique that number of circulating times is large and encrypting efficiency is low, simplifying the chip design, largely optimizing integrity of chip signal and being able to improve interference immunity of system and reduce system cost.

High-efficient encryption and decryption processing method for implementing SMS4 algorithm

An encryption and decryption processing method, system and computer-accessible medium for achieving SMS4 cryptographic procedure/algorithm can be provided. First, constant arrays can prepared, the external data are input into a data registering unit and the first data conversion is addressed. Secondly, the second data conversion is addressed. Thirdly, the second data conversion is repeated until completing all the prescribed data conversion. Then, the results of repeating encryption and decryption processing are achieved.

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Xi'an, China

Jiayin Lu