Maxlinear, Inc.

Intel Corporation

Infineon Technologies Ag

Intel Germany Gmbh & Co. Kg

Jiaxiang Shi

Ingo Volkening

Ritesh Banerjee

Qiming Wu

Chunfeng Hu

Chun Feng Hu

Hong Lee Koo

Sachin Mathur

Yao Chye Lee

Jasmeet Singh Narang

Vinay Sharma

Chuanhua Lei

Ravindar Attineni

Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.

Memory management device for performing DMA operations between a main memory and a cache memory

Examples relate to apparatuses, devices, methods and computer programs for a Root Complex (RC) and/or for an Endpoint (EP) of a PCIe (Peripheral Component Interconnect express) system, to a PCIe system and to a gateway device comprising a PCIe system. An apparatus configured for a RC of a PCIe system comprises a memory and one or more processors, which are configured to generate a PCIe VDM (Vendor Defined Message) message for an EP of the PCIe system.

System communication technique over PCIe® (peripheral component interconnect express) link

A boot read only memory (ROM) chip unit can perform a secure boot routine based on various operations. A processor device comprises a boot ROM chip with processing circuitry on a system board configured to perform a system board power up according to a read operation in a one-time-programmable OTP memory/non-volatile memory (NVM). The OTP memory/NVM includes a spare area in a portion of the OTP/NVM that can receive a first sequence pattern. The processor determines whether a secure boot indication indicates a secure boot routine, and differentiates one or more read return content of the OTP memory/NVM between a wrongly read return content and a trusted read return content, in response to, or concurrent with, the secure boot indication indicating the secure boot routine.

Non-volatile-memory (NVM) contents read return validation

Memory management device containing memory copy device with direct memory access (DMA) port

Anti-fault injection systems and methods are disclosed. An anti-fault injection system includes a processor; a boot ROM configured to store a series of boot instructions executable by the processor; and anti-fault injection controller circuitry. The anti-fault injection controller circuitry is accessible to the processor while the processor is executing the boot instructions. The anti-fault injection controller circuitry includes interrupt/reset circuitry configured to interrupt the processor in response to a trigger and secure boot circuitry. The secure boot circuitry is configured to, in response to being accessed by the processor: determine whether the processor is executing non-secure boot instructions in error; and in response to detecting that the processor is executing non-secure boot instructions in error, provide the trigger to the interrupt/reset circuitry.

Hardware assisted fault injection detection

A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.

Systems and methods for dynamic phase alignment of clocks

Systems, methods, and circuitries adapt a system-on-chip (SoC) for use with different external devices. In one example, an SOC includes a plurality of SoC data lanes configured to conduct data signals between the SoC and an external device interface. The SoC also includes an interface lane adaptor and a device interface including a plurality of interface connectors. The interface lane adaptor circuitry includes a plurality of SoC adaptor connectors connected to the interface connectors; a plurality of external adaptor connectors connected to the SoC data lanes and configured to be connected to the external device interface; a lane selector circuitry configured to connect a selected one of a first or a second SoC adaptor connector to a selected SoC data lane; and a lane configuration circuitry configured to control the lane selector circuitry to connect either the first or the second SoC adaptor connector to the selected SoC data lane.

Selective data lane interface mapping

There is provided an apparatus and method for ATM bonding. The apparatus comprises a first unit having a first xDSL line connected thereto, a second unit having a second xDSL line connected thereto and a connection between the first unit and the second unit. The first unit is arranged to convert one incoming ATM datastream to a plurality of data and to convert a plurality of incoming data to one ATM data stream. The first unit is arranged to implement the ATM bonding layer of the ATM protocol. The second unit may be arranged to implement one or more of the higher layers. The method comprises the steps of: a first unit receiving an ATM data stream; the first unit converting the ATM data stream into a plurality of data; the first unit transmitting a first one of the plurality of data over a first xDSL line connected to the first unit; the first unit sending a second one of the plurality of data to a second unit via a connection; and the second unit transmitting the second one of the plurality of data over a second xDSL line connected to the second unit.

ATM bonding

There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.

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Singapore, Singapore

Jiaxiang Shi