Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Jiawen Zhang

Jun Cao

Ali Nazemi

Adesh Garg

Afshin Momtaz

Delong Cui

Anand Jitendra Vasani

Meisam Honarvar Nazari

Kun Chuai

Hyo Gyuem Rhew

Jan Mulder

Tamer Mohammed Ali

Jan Roelof Westra

Burak Catli

An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.

Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers

A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.

Clock skew suppression for time-interleaved clocks

Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.

Multiplexer circuit for a digital to analog converter

A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Multi-segmented all logic DAC

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

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Irvine, CA, United States of America

Jiawen Zhang