United Semiconductor (xiamen) Co., Ltd.

Jiawei Lyu

Wen Yi Tan

Guang Yang

Linshan Yuan

Chin-Chun Huang

Jinjian Ouyang

Jung-Chun Yen

Chien-Chih Wang

The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Semiconductor testkey pattern and test method thereof

A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.

Semiconductor memory device

Growing community of inventors

Quanzhou, China

Jiawei Lyu