Nxp Usa, Inc.

Jiawei Fu

Jie Jin

Jianzhou Wu

Stefano Pietri

Liang Zhang

Yang Wang

Michael Todd Berens

Yizhong Zhang

Yikun Mo

Yan Huang

Jianluo Chen

Hongyan Yao

A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fbased on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fwith a high frequency clock having a constant frequency f. A memory is included to store at least two counter values generating by comparing fand fonce when the LSB side resistor network is connected while the MSB side resistor network is floating and once when the LSB side resistor network is floating while only one of the resistors in the MSB side resistor network is connected and all other resistors in the MSB side resistor network are floating. A comparator is included to compare the at least two counter values. A trimming controller is included to generate a trimming signal to trim one of the plurality of trimmable resistors based on an output of the comparator.

Self calibrating digital-to-analog converter

A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.

Bias current generator circuit

A buffer stage for amplifying a clock signal generated by a current controlled oscillator that receives a first current at a first supply voltage from a first current source. The buffer stage comprises an input terminal configured to receive the clock signal; an output terminal configured to output a buffered signal; at least one buffer, coupled between the input and output terminal, configured to receive a second current at a second supply voltage and buffer the clock signal to generate the buffered signal; a clamping circuit that receives the first current and the second current, and generates a first supply voltage and a second supply voltage. The clamping circuit clamps the second supply voltage equal to the first supply voltage.

Buffer stage for use with a current controlled oscillator

A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Clock generator and method for generating clock signal

A start-up circuit for a ring current-controlled oscillator (CCO) includes a replica CCO current generator, a replica ring CCO, and a buffer. The ring CCO is connected to a CCO driver and the buffer. The CCO driver generates a CCO current based on a reference current. The ring CCO generates a CCO output voltage at a first oscillating frequency based on the CCO current. The replica CCO current generator generates a replica CCO current based on a reference voltage. The replica ring CCO generates a replica CCO output voltage at a second oscillating frequency based on the replica CCO current. The buffer provides a first current to the ring CCO when the first oscillating frequency is lower than a desired oscillating frequency, and drains a second current from the ring CCO when the first oscillating frequency is greater than the desired oscillating frequency.

Growing community of inventors

Suzhou, China

Jiawei Fu