Yangtze Memory Technologies Co., Ltd.

Jiawei Chen

Chunyuan Hou

Qiang Tang

Shu Xie

Yueping Li

Yi Gu

Wenjie Mu

The implementation of the present disclosure provides a memory, an operation method thereof and a memory system. For example, the memory can include a first memory plane, a second memory plane, and a plane data bus connected to each of the first memory plane and the second memory plane. The plane data bus can be configured to receive input data. The first memory plane can be configured to store first data of the input data. The second memory plane can be configured to store second data of the input data. The second data can be configured to indicate whether the first data has been performed with an inversion operation prior to transmission.

Memory and an operating method thereof, a memory system

An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.

3D NAND flash memory device and integration method thereof

A memory device includes a memory array, a first buffer, a second buffer, a repair logic circuit and an internal memory. The method of operating the memory device includes: the repair logic circuit receiving a bad column table from the internal memory, the bad column table containing information of a bad column in the memory array; the first buffer receiving first data; the repair logic circuit receiving the first data from the first buffer; and the repair logic circuit mapping the first data onto second data according to the bad column table.

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Wuhan, China

Jiawei Chen