Sandisk Technologies Inc.

Jianzhi Wu

Xiang Yang

Yanjie Wang

Deepanshu Dutta

Gerrit Jan Hemink

Huai-Yuan Tseng

Henry Chin

Jun Wan

Guirong Liang

Jia Li

A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

Power saving and fast read sequence for non-volatile memory

An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

Peak current and program time optimization through loop dependent voltage ramp target and timing control

A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

Dynamic bit line voltage and sensing time enhanced read for data recovery

A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.

Positive feedback and parallel searching enhanced optimal read method for non-volatile memory

Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.

Mitigating grown bad blocks

An apparatus comprising strings of non-volatile memory cells is disclosed. Each string comprises non-volatile memory cells, an operative select gate, and a dummy select gate. The apparatus comprises a select line connected to the operative select gate of each string, and a dummy line connected to the dummy select gate of each string. The dummy line is an immediate neighbor to the select line. The apparatus comprises a control circuit configured to apply a voltage waveform to the select line while the dummy line is floating. The control circuit is configured to detect a floating voltage on the dummy line while applying the voltage waveform to the select line. The control circuit is configured to determine a condition of the voltage waveform at a target location on the select line based on the floating voltage on the dummy line.

Select line voltage waveform real-time monitor for non-volatile memory

A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

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Milpitas, CA, United States of America

Jianzhi Wu