Intel Corporation

Jianyong Xie

Sujit Sharan

Kemal Aygun

Andrew Paul Collins

Zhiguo Qian

Debendra Mallik

Yidnekachew S Mekonnen

Robert L Sankman

Zhichao Zhang

Mathew J Manusharow

Lijiang Wang

Aleksandar Aleksov

Henning Braunisch

Saikumar Jayaraman

Shigeki Tomishima

Xiaohong Jiang

Arghya Sain

Prasad Ramanathan

Yí Li

Hector Amador

Huang-Ta Chen

Biancun Xie

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.

Substrateless double-sided embedded multi-die interconnect bridge

Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

EMIB architecture with dedicated metal layers for improving power delivery

Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

Semiconductor packages with chiplets coupled to a memory device

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Power delivery for embedded bridge die utilizing trench structures

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

Capacitor die embedded in package substrate for providing capacitance to surface mounted die

An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

Dielectric-filled trench isolation of vias

Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

Horizontal pitch translation using embedded bridge dies

Embodiments herein relate to systems, apparatuses, or processes for an interconnect hub for dies that includes a first side and a second side opposite the first side to couple with three or more dies, where the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies to another of the three or more dies to facilitate data transfer between at least a subset of the three or more dies. The three or more dies may be tiled dies.

Interconnect hub for dies

An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

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Chandler, AZ, United States of America

Jianyong Xie