Yangtze Memory Technologies Co., Ltd.

Jianquan Jia

Kaikai You

Ying Cui

Yali Song

Kaiwei Li

XiangNan Zhao

Shan Li

An Zhang

Lei Jin

Hongtao Liu

Yuanyuan Min

Xinlei Jia

Xueqing Huang

Jinlong Zhang

Yuan-Yuan Min

Meng Lou

Feng Xu

Da Li

Junbao Wang

Zhe Luo

Pan Xu

Kun Yang

Chenhui Li

Xuezhun Xie

Wen Zhou

Wei Qi

Wei Hou

Zhiyu Wang

Kun Fan

Jiayin Han

Yaoyao Tian

A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

Non-volatile memory device and control method

The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Memory devices and operating methods thereof, memory systems

In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Method of reducing program disturbance in memory device and memory device utilizing same

A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.

Programming method for semiconductor device and semiconductor device

The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.

Control method for memory erase operations, apparatus, and storage medium thereof

The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

Method of improving programming operations in 3D NAND systems

A three-dimensional (3D) memory device includes a first set of word lines coupled to first memory cells, a second set of word lines coupled to second memory cells, an interface dummy word line between the first and send sets of word lines, and a peripheral circuit coupled to the first and send memory cells. The peripheral circuit is configured to apply a first voltage to the interface dummy word line in a first pre-charge period when programming a first selected memory cell in the first memory cells, and apply a second voltage lower than the first voltage to the interface dummy word line in a second pre-charge period when programming a second selected memory cell in the second memory cells. Programing the first selected memory cell is earlier than the second selected memory cell.

Three-dimensional memory device programming with reduced disturbance

A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.

Method of performing programming operation and related memory device

A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Method of programming memory device and related memory device

The present disclosure provides systems, methods and media of optimization of temporary read errors (TRE) in three-dimensional (3D) NAND memory devices. The (3D) NAND memory devices comprises a plurality of memory cells arranged as an array of NAND memory strings, a plurality of word lines couple to the memory cells, and a controller. The controller is configured to determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and in response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation.

Systems, methods and media of optimization of temporary read errors in 3D NAND memory devices

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

Memory device and erasing and verification method thereof

A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.

Three-dimensional memory and control method thereof

A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Method and memory used for reducing program disturbance by adjusting voltage of dummy word line

A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.

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Wuhan, China

Jianquan Jia