Semiconductor Manufacturing International (shanghai) Corporation

Delta Electronics, Inc.

Jianping Yang

Jieguang Huo

Hong Iris Zhu

Chunyan Xin

Yanyong Wang

Jianping Ying

Herb He Huang

Roger Lee

Jingtao Tan

Zhijian Zhou

Jie Guang Huo

Chun Yan Xin

Chunyun Xin

Wenhui Gou

Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region.

Method and system for CMOS image sensing device

The configurations of a single-phase dual buck-boost/buck power factor correction (PFC) circuit and a controlling method thereof are provided in the present invention. The proposed circuit includes a single-phase three-level buck-boost PFC circuit receiving an input voltage and having a first output terminal, a neutral-point and a second output terminal for outputting a first and a second output voltages, a single-phase three-level buck PFC circuit receiving the input voltage and coupled to the first output terminal, the neutral-point and the second output terminal, a first output capacitor coupled to the first output terminal and the neutral-point, a second output capacitor coupled to the neutral-point and the second output terminal, and a neutral line coupled to the neutral-point.

Single-phase and three-phase dual buck-boost/buck power factor correction circuits and controlling method thereof

A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

Method and device for CMOS image sensing with multiple gate oxide thicknesses

An image sensor includes an array of photo-sensing regions formed in a semiconductor substrate, a dielectric layer over the array of photo-sensing regions, and an array of microlenses formed in the dielectric layer. Each of the microlenses is center-aligned over one of the photo-sensing regions and has a truncated plano-convex shape. The microlenses have an index of refraction that is higher than the dielectric layer's refraction index. Each of the microlenses has a smooth circular top, a flat circular bottom, and a curved circumferential side convex towards the semiconductor substrate.

Method and system of embedded microlens

A complementary metal oxide semiconductor (CMOS) image sensing device includes a semiconductor substrate; a photodiode defined on the substrate; a gate dielectric layer provided over the photodiode and the substrate; a polysilicon interconnect contacting a given area of the photodiode via an opening in the gate dielectric layer; a reset transistor coupled to the photodiode; a source follower transistor coupled to the photodiode; and a select transistor coupled to the source follower transistor. The given area of the photodiode defines a node that is coupled to the reset transistor and source follower transistor.

CMOS image sensor

A method for fabricating CMOS image sensor device includes providing a P-type semiconductor substrate. The semiconductor substrate includes a surface region. The method includes forming a first dielectric layer having a first thickness overlying a first region of the semiconductor substrate. The method includes providing an N type impurity region in a portion of the semiconductor substrate underneath the first dielectric layer to cause formation of a photodiode device region characterized by at least the N type impurity region and the P type substrate. A second dielectric layer having a second thickness is formed in a second region of the surface region. The second dielectric layer is formed within a portion of the first region within the first thickness of the first dielectric layer. The method includes forming a polysilicon gate layer overlying at least the second region to form a contact member coupled to the second region.

Method of interconnect for image sensor

A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surface region and forming a first gate structure overlying a first portion of the gate oxide layer, the first gate structure has a top surface region and at least a side region. The method forms an N-type impurity region in a portion of the semiconductor substrate to form a photodiode device region from the N-type impurity region and the P-type impurity. The method includes forming a blanket spacer layer including an oxide on nitride on oxide structure overlying at least the first gate structure; and forming one or more spacer structures using the blanket spacer layer for the first gate structure while maintaining a portion of the oxide layer from the oxide on nitride on oxide overlying at least the photo-diode device region.

ONO spacer etch process to reduce dark current

A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method forma first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate.

Method and structure for a CMOS image sensor using a triple gate process

The present invention provides a method for fabricating a pixel cell of CMOS image sensor, comprising: preparing a semiconductor substrate divided into region I and region II; forming an insulation layer on the surface of the semiconductor substrate in the region I and a gate dielectric layer on the surface of the semiconductor substrate in the region II; forming a poly-silicon gate on the surface of the semiconductor substrate in the region II; forming a deep doped well in the region I through an ion implantation with high energy; performing an ion implantation with low energy in the region I and an ion implantation for lightly doped source/drain in the region II simultaneously; and forming source/drain regions in the semiconductor substrate in the region II.

Method for fabricating pixel cell of CMOS image sensor

Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide. The second metal layer is removed by etching.

Method of making CMOS image sensor-hybrid silicide

Method of making CMOS image sensor&#x2014;hybrid silicide

A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well.

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Shanghai, China

Jianping Yang