Avnera Corporation

Synopsys, Inc.

Jianping Wen

Wai Laing Lee

Garry Link

John Theodore Stonick

Daniel Keith Weinlader

David Andrew Yokoyama-Martin

Skye Wolfer

James P Flynn

Junqi Hua

Amit Kumar

Wai Lang Lee

Eric T King

Ali Hadiashar

David W Entrikin

Richard H Steeves

Robert Beverly Lefferts

Gordon Ueki

Dino Anthony Toffolon

Xudong Zhao

Jasjeet Singh

Garry N Link

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port.

Digitally calibrated successive approximation register analog-to-digital converter

The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

Hybrid flash architecture of successive approximation register analog to digital converter

Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Analog to digital converters with oversampling

The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

Programmable sequence controller for successive approximation register analog to digital converter

The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

Chopper stabilized comparator for successive approximation register analog to digital converter

The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

Reference disturbance mitigation in successive approximation register analog to digital converter

A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors C[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vand the digital output port.

An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.

Noise cancellation system

A circuit can include a voltage comparator Vhaving a first input, a second input, and an output; a first plurality of capacitors C[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V, wherein each top plate is also switchably electrically coupled with a common mode voltage V, and wherein each bottom plate is switchably electrically coupled between a first input voltage V, a reference voltage V, the common mode voltage V, and ground; a second plurality of capacitors C[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V, wherein each top plate is also switchably electrically coupled with the common mode voltage V, and wherein each bottom plate is switchably electrically coupled between a second input voltage V, the reference voltage V, the common mode voltage V, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.

A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in&#x2014;feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.

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Beaverton, OR, United States of America

Jianping Wen