Chengdu Boe Optoelectronics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Boe Technology Group

Jianpeng Wu

Chang Luo

Fengli Ji

Ming Hu

Qian Xu

Peng Xu

Yan Huang

Benlian Wang

Tong Niu

Zhiliang Jiang

Tianyi Cheng

Ziyang Yu

Wenbo Chen

Zhongying Yang

Haijun Qiu

Mengqi Wang

Guomeng Zhang

Lujiang Huangfu

Cong Liu

Sen Du

Wei Zhang

Tiaomei Zhang

Erjin Zhao

Yi Zhang

Yuanqi Zhang

Yinan Liang

Pan Zhao

Quanyong Gu

Qingqing Yan

Xiaoyu Yang

Qing He

Xiangnan Pan

Weiwei Ding

Sifei Ai

Libin Liu

Jie Zhang

Song Zhang

Pinfan Wang

Chunyan Xie

Yu Xin Zhao

Yi Qu

Kuo Sun

Hongli Wang

Jian He

Haidong Wu

Penghao Gu

Mei Li

Ge Wang

Yonglin Guo

Xilei Cao

Xiaodan Jin

Long Ma

Wenbiao Ding

Wenbo Hu

Ju Mei

Xiaoliang Guo

Yongjie Song

Panting He

Guodong Zhang

Jianbo Li

Lan Lan

Qi Wei

Yi Ma

A drive control circuit includes an input circuit, a first output circuit and a first output control circuit. An input circuit is configured to control the potentials of a first node and a second node under the control of a signal input terminal and a clock signal terminal. The first output circuit is configured to provide a first power supply signal to a third node under the control of a first node or to provide a second power supply signal to a first output terminal under the control of a second node. The first output control circuit is configured to turn on or turn off the third node and the first output terminal under the control of the first control terminal.

Drive control circuit, gate drive circuit and display panel

There is provided a display panel, including: pixel units arranged in an array; each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel emitting light of different colors and having areas sequentially increased; along a column direction of the array, for any adjacent pixel units, the second sub-pixel of the former pixel unit is arranged adjacent to the first sub-pixel of the latter pixel unit; third sub-pixels in the adjacent pixel units are arranged in sequence; a minimum distance and a maximum distance exist between the third sub-pixels adjacent to each other in the adjacent pixel units; for any adjacent pixel units, the second sub-pixel of the former pixel unit and the first sub-pixel of the latter pixel unit, which are adjacent to each other, are kept apart by a first distance being greater than the minimum distance and less than the maximum distance.

Display panel, display device and mask

The present disclosure provides a display substrate and related devices. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.

Display substrate and related devices with improved resolution

Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Display substrate, display device and high-precision metal mask

A driving circuit includes a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; N is a positive integer; the first gating circuit controls to write the gating input signal into the first first node under the control of the gating control signal; the first output circuit controls to connect the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controls to connect the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; the first third control node and the first second control node are different nodes.

Driving circuit, driving method, driving module and display device

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

Gate driving circuit having a gating circuit, and driving method thereof

A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

Shift register, driving method, gate drive circuit and display device

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; the driving signal generation circuit generates and outputs the Nth stage of driving signal; the gating circuit controls to write the gating input signal into the first node; the output control circuit performs a NAND operation on the Nth stage of driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal; the output circuit inverts the first output signal to obtain and provide an output driving signal through the output driving terminal; N is a positive integer.

A display substrate and a mask plate assembly includes a base substrate, a pixel defining layer, a functional layer, a cathode layer, and a covering layer that are sequentially stacked in a direction away from the base substrate, wherein the size of orthographic projection of the functional layer on the base substrate is jointly determined by the size of a display area and a first minimum distance. The first minimum distance is the minimum distance in a direction from the display area to a non-display area and between the boundary of the display area and the boundary of the functional layer, and is determined by a first shadow width of the functional layer extending from the display area to the non-display area. The first shadow width is the maximum width of a shadow area formed within a preset region when the functional layer is vapor deposited in the preset region.

Display substrate and mask plate assembly

A driving circuit, a driving method, a driving module and a display device are provided. The driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a third control node control circuit. The third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a second node control circuit; the driving signal generation circuit generates an Nth stage of driving signal; the output control circuit controls to connect the first control node and the second node under the control of the potential of the first node; the gating circuit writes a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to the potential of the first node; the second node control circuit controls to connect the second node and the first voltage terminal under the control of the potential of the first node.

A pixel array includes a plurality of sub-pixels, which include first to third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form first pixel rows. The first and third sub-pixels, which are in a same column, in the first pixel rows are alternately arranged, and the second sub-pixels are arranged side by side along the row direction and form second pixel rows. Lines sequentially connecting centers of two of the first sub-pixels and two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. A straight line in the row direction or in a column direction, which passes through a center of each sub-pixel of at least one of the plurality of sub-pixels, divides the sub-pixel into two parts having areas different from each other.

Pixel array and display device

The present disclosure provides a driving circuitry, a driving method, a driving module, and a display device. The driving circuitry includes a driving signal generation circuitry, a gating circuitry, an output control circuitry and an output circuitry. The driving signal generation circuitry is configured to perform a shifting operation on an (N−1)-level driving signal to obtain an N-level driving signal. The gating circuitry is configured to write a gating input signal into a first node under the control of a gating control signal. The output control circuitry is configured to perform an NAND operation on the N-level driving signal and a potential at a second end of the output control circuitry to obtain a first output signal. The output circuitry is configured to perform phase inversion on the first output signal to obtain and provide an output driving signal through an output driving end, where N is a positive integer.

Driving circuitry, driving method, driving module, and display device

The present disclosure relates to a mask, a mask device and a mask design method. The mask includes: a pattern area, wherein the pattern area includes a plurality of openings, among which adjacent openings are spaced apart by a first rib, and at least one of the plurality of openings has a non-straight side, two first straight sides intersecting with the non-straight side, and a second straight side opposite to the non-straight side and intersecting with the first straight sides; and a second rib located at an edge of the pattern area, wherein the second rib is provided with a cutout for compensating for stretch deformation of the non-straight side, extending lines of the two first straight sides extending toward the second rib along a first direction intersect with the second rib to obtain a first area, and the cutout is located at least within the first area.

Mask, mask device and mask design method

A display substrate and a display device are provided. The display substrate includes a plurality of repeat units. Each of the plurality of repeat units includes one first-color sub-pixel, one second-color sub-pixel pair and one third-color sub-pixel which are arranged in a first direction, the second-color sub-pixel pair includes two second-color sub-pixels arranging in a second direction. Connecting lines of centers of orthographic projections of light-emitting regions of four second-color sub-pixels on the base substrate form a first trapezoid, and at least one edge of the first trapezoid is located outside orthographic projections of light-emitting regions of respective sub-pixels on the base substrate.

Display substrate and display device

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Beijing, China

Jianpeng Wu