Taiwan Semiconductor Manufacturing Comp. Ltd.

Comp-any Gmbh

Jiann-Tyng Tzeng

Shih-Wei Peng

Wei-Cheng Lin

Kam-Tou Sio

Charles Chew-Yuen Young

Chih-Liang Chen

Chih-Ming Lai

Ru-Gun Liu

Wei-An Lai

Te-Hsin Chiu

Hui-Ting Yang

Chia-Tien Wu

Hui-Zhong Zhuang

Lei-Chun Chou

Chun-Kuang Chen

Cheng-Chi Chuang

Lipen Yuan

Meng-Hung Shen

Shang-Wei Fang

Chew-Yuen Young

Wei-Liang Lin

Chin-Yuan Tseng

Ching-Yu Huang

Ching-Wei Tsai

Yi-Hsun Chiu

Pin-Dai Sue

Guo-Huei Wu

Shun Li Chen

Kam-tou Sio

Yi-Kan Cheng

Wen-Hao Chen

Jack Liu

Yung-Sung Yen

Chi-Yeh Yu

Yu-Xuan Huang

Shun-Li Chen

Yan-Hao Chen

L C Chou

Te-hsin Chiu

Li-Chun Tien

Tien-Lu Lin

Wei-Hao Wu

Chung-Hsing Wang

Yuh-Hwa Chang

Chun-Hung Liou

Meng-hung Shen

Chia-Hao Chang

Lee-Chung Lu

Shi Ning Ju

Ta-Pen Guo

David Barry Scott

Yi-Hsiung Lin

Hsin-Chih Chen

Wei-Chen Chien

Sing-Kai Huang

Kuan-Lun Cheng

Kuo-Cheng Chiang

Yen-Ming Chen

Ting-Wei Chiang

Stefan Rusu

Huan-Chieh Su

Chun-Yuan Chen

Ken-Hsien Hsieh

Hou-Yu Chen

Chung-Cheng Wu

Jung-Chan Yang

Min Cao

Hsiang-Jen Tseng

Yi-Bo Liao

Shyue-Shyh Lin

Ching-Fang Huang

Po-Chia Lai

Chih-Min Hsiao

Shyh-Wei Wang

Sheng-Jier Yang

Yi-Feng Chen

Ali Keshavarzi

Kuo-Cheng Ching

Sang Hoo Dhong

Kuo-Ming Wu

Hsin-Chieh Huang

Kuan-Yu Chen

Yuan-Te Hou

Shang-Chih Hsieh

Chih-Chieh Yeh

Shang-Wen Chang

Yi-Ming Sheu

Kuan-lun Cheng

Chun-Fu Cheng

Chen-Bau Wu

Yi-Chuin Tsai

Hou-yu Chen

Ching-Hsu Chang

Chun-Yen Lin

Ching-Wen Cho

Yi-Han Wang

Shu-Hui Sung

David Ho

Haw-Chuan Wu

A method includes: forming a first channel structure through a first gate structure; forming a first source/drain structure coupled to the first channel structure at a first surface of the first gate structure; before the first source/drain structure is formed, forming a first isolation layer at a second surface of the first gate structure to isolate the first channel structure; and after the first source/drain structure is formed, forming a first insulation structure at a position of the first isolation layer. The first surface and the second surface are opposite to each other, and a size of the first insulation structure is equal to or larger than a size of the first source/drain structure.

Semiconductor device and manufacturing method thereof

A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

Semiconductor device

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a second electrical conductor, a third electrical conductor, a plurality of metal features and a plurality of active regions. The first electrical conductor extends along a first direction and is electrically coupled to a first voltage. The second electrical conductor extends along the first direction and is electrically coupled to a second voltage. The second voltage is lower than the first voltage. The third electrical conductor extending along the first direction is electrically coupled to a third voltage and disposed between the first electrical conductor and the second electrical conductor. The metal features extend along a second direction perpendicular to the first direction and are formed above the first electrical conductor, the second electrical conductor and the third electrical conductor.

Semiconductor device and method of manufacturing the same

An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

Integrated circuit having hybrid sheet structure

A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.

A device including first nanosheet structures each including a first number of nanosheets, second nanosheet structures each including a second number of nanosheets that is different than the first number of nanosheets, and a plurality of rows including first rows and second rows. Where each of the first nanosheet structures is in a respective one of the first rows, each of the second nanosheet structures is in a respective one of the second rows, at least two of the first rows are adjacent one another, and at least two of the second rows are adjacent one another.

APR placement for hybrid sheet cells

An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Backside conductive segments cover a first active region and define an opening above a second active region

Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Methods for generating a circuit with high density routing layout

An integrated circuit includes a first power rail, a second power rail, and a power tap cell. The first power rail is at a first side of the integrated circuit. The second power rail is at a second side of the integrated circuit. The first and second sides are on opposite sides of at least a complementary field effect transistor. The power tap cell is coupled to the first power rail and the second power rail and configured to provide power from the first power rail to the second power rail.

Integrated circuits and methods for power delivery

A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

Semiconductor device including vertical transistor with back side power structure

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first active region disposed on the substrate, a first gate structure disposed on the first active region, and a second gate structure disposed on the first active region and spaced apart from the first gate structure. The first active region includes a first portion and a second portion, the first portion of the first active region and the second portion of the first active region collectively specify a first stair profile. The first stair profile is located between the first gate structure and the second gate structure from a top view.

Semiconductor device having active regions of different dimensions and method of manufacturing the same

An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Integrated circuit

An integrated circuit includes metal rails. The integrated circuit includes a first layer including a first metal rail and a second layer including a second metal rail, where the second layer is above the first layer along a first direction. The integrated circuit includes a third layer including an active region of a transistor, where the third layer is above the second layer along the first direction. The integrated circuit includes a fourth layer including a third metal rail, where the fourth layer is above the third layer along the first direction. The integrated circuit includes a fifth layer including a fourth metal rail, where the fifth layer is above the fourth layer along the first direction.

Integrated circuit with backside power rail and backside interconnect

A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.

Multiple back side/buried power rail (BPR) cell including field-effect transistors with air void between two adjacent BPR cells

Growing community of inventors

Hsinchu, Taiwan

Jiann-Tyng Tzeng