Micron Technology Incorporated

Nan Ya Technology Corporation

Jianming Zhou

Anton J deVillers

Scott L Light

Yuan He

Dan B Millward

Kaveri Jain

Zishu Zhang

Michael D Hyatt

Lijing Gou

Richard T Housley

Justin B Dorhout

David A Kewley

Craig A Hickman

Ranjan Khurana

Prasanna Srinivasan

David Swindler

Erik R Byers

Anton J De Villiers

Denzil S Frost

Volodymyr Temchenko

Hongqian Sun

A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.

Integrated-circuitry overlay alignment mark, a substrate comprising an overlay alignment mark, a method of forming an overlay alignment mark in the fabrication of integrated circuitry, and a method of determining overlay alignment in the fabrication of integrated circuitry

Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.

Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings

Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Semiconductor constructions and methods of forming semiconductor constructions

Disclosed are cooling apparatus and methods of cooling a template. The cooling apparatus includes a reticle and an optical cooling material. The reticle includes patterning for at least partially reflecting patterning radiation incident on a first side of the reticle. The optical cooling material is in thermally-conductive coupling with the reticle mount and is configured to produce cooling when exposed to a laser radiation. More particularly, the optical cooling material includes a glass material that exhibits anti-Stokes fluorescence that produces cooling of the glass material when exposed to an infrared laser beam. In some embodiments, the cooling apparatus may be incorporated with a reticle mount. The reticle mount is in thermally-conductive coupling with a second side of the reticle.

Methods and apparatuses for template cooling

Photolithographic apparatus and methods are disclosed. One such apparatus includes an optical path configured to provide a first diffraction pattern in a portion of an optical system and to provide a second diffraction pattern to the portion of the optical system after providing the first diffraction pattern. Meanwhile, one such method includes providing a first diffraction pattern onto a portion of an optical system, wherein a semiconductor article is imaged using the first diffraction pattern. A second diffraction pattern is also provided onto the portion of the optical system, but the second diffraction pattern is not used to image the semiconductor article.

Lens heating compensation in photolithography

Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

Lithography methods, methods for forming patterning tools and patterning tools

An imaging device comprising a first region and a second region. Imaging features in the first region and assist features in the second region are substantially the same size as one another and are formed substantially on pitch. Methods of forming an imaging device and methods of forming a semiconductor device structure are also disclosed.

Imaging devices, methods of forming same, and methods of forming semiconductor device structures

An overlay mark for checking alignment accuracy between a former layer and a later layer on a wafer is described, including a former pattern as a part of the former layer, and a later pattern as a part of a patterned photoresist layer defining the later layer. The former pattern has two parallel opposite edges each forming a sharp angle &#x3b1; with the x-axis of the wafer. The later pattern also has two parallel opposite edges each forming the sharp angle &#x3b1; with the x-axis of the wafer.

Overlay mark and application thereof

A reticle with a composite polarizer includes: a transparent substrate; a patterned layer disposed on said transparent substrate; and a polarizing filter disposed on said transparent substrate, wherein said transparent substrate is substantially transparent with respect to illumination light, said patterned layer is partially opaque with respect to said illumination light, and said polarizing filter is capable of selectively polarizing said illumination light.

Reticle with composite polarizer and method of simultaneous optimization of imaging of a set of different patterns

A method of mitigating asymmetric lens heating in photolithographically patterning a photo-imagable material using a reticle includes determining where first hot spot locations are expected to occur on a lens when using a reticle to pattern a photo-imagable material. The reticle is then fabricated to include non-printing features within a non-printing region of the reticle which generate additional hot spot locations on the lens when using the reticle to pattern the photo-imagable material. Other implementations are contemplated, including reticles which may be independent of method of use or fabrication.

Reticles, and methods of mitigating asymmetric lens heating in photolithography

Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Semiconductor constructions and methods of forming patterns

Methods of forming semiconductor constructions

Some embodiments include system and methods to obtain information for adjusting variations in features formed on a substrate of a semiconductor device. Such methods can include determining a first pupil in an illumination system used to form a first feature, and determining a second pupil used to form a second feature. The methods can also include determining a pupil portion belonging to only one of the pupils, and generating a modified pupil portion from the pupil portion. Information associated with the modified pupil portion can be obtained for controlling a portion of a projection lens assembly of an illumination system. Other embodiments are described.

Lithography wave-front control system and method

A method of processing a substrate includes forming first photoresist on a substrate. A portion of the first photoresist is selectively exposed to actinic energy and then the first photoresist is negative tone developed to remove an unexposed portion of the first photoresist. Second photoresist is formed on the substrate over the developed first photoresist. A portion of the second photoresist is selectively exposed to actinic energy and then the second photoresist is negative tone developed to remove an unexposed portion of the second photoresist and form a pattern on the substrate which comprises the developed first photoresist and the developed second photoresist. Other implementations are disclosed.

Growing community of inventors

Boise, ID, United States of America

Jianming Zhou