Sino Ic Technology Co., Ltd.

Jianming Ye

Hua Wang

Bin Luo

Xuefei Tang

Shouyin Ye

Jianbo Ling

A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

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Pudong New Area, China

Jianming Ye