Cadence Design Systems, Inc.

Jianmin Li

Stefanus Mantik

Vassilios Constantinos Gerousis

Shuo Zhang

Jing Yang Chen

Taufik Arifin

Yuan Huang

Soohong A Kim

Ming Zhang

Gang Huang

Ting Li

Limin He

Jimmy Kwok-Ching Lam

Dennis Huang

Dahe Chen

Louis Tsai

Dewi Farrah Santoso

Ganping Sun

Pujiang Huang

Shane Zhang

Guowei Zhao

An approach includes a new power and ground structure description language (PSDL) will allow the user to describe the desired routing pattern for each layer and on a user defined region by region basis, including how the pattern will be laid out in the design with respect to other patterns from a different layer. The new PSDL also gives the complete picture of the entire power and ground structure, instead of just a layer-by-layer view from a single command. It also allowed flexibility in alignment especially when dealing with track misalignments, thus avoiding the extensive trial-and-error steps needed to calculate offsets and distances to maintain pattern alignment using previous approaches. Additionally, because PSDL is not tightly dependent on the design size and/or floorplan, transferring the desired power and ground structure from one design to another will be very easy with only few adjustments.

Pattern-based formal description language for describing a power/ground routing structure in an integrated circuit design

An improved approach is described to implement trim data representation for an electronic design. Instead of maintaining a gap shape object for every gap in the layout, existing objects adjacent to the gap location are configured to include attributes of the gap shape. The properties of the gap shape can then be derived from the adjacent objects.

Method and system for implementing efficient trim data representation for an electronic design

One aspect identifies an interconnect and associated design rule(s) and moves a portion of the interconnect to an adjacent track by using a spreading process on a one-dimensional design data based on the design rule(s) to determine whether the interconnect including the moved portion provides a DRC clean implementation. This aspect examines an interconnect in its entirety without being confined within a prescribed boundary of a fixed region in the layout. The one-dimensional design data provides expedient runtime and may be converted back into two-dimensional form for the layout. Another aspect iterates through multiple spreading distances to route or modify interconnects in a layout by performing multiple Boolean operations on the interconnect and adjacent shape(s) to determine the final form of the newly created or modified interconnect complying with various design rules.

Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques

Disclosed are methods, systems, and articles of manufactures for implementing correct-by-construction physical designs with multiple-patterning-awareness by identifying a first set of grids for a layer based at least in part upon characteristics of other layer(s), identifying a set of tracks for the layer to implement the physical design for the layer, and implementing a shape in the physical design by at least terminating an end of the shape at a grid of the identified first set of grids. The end of the shape may be extended or contracted from its as-design location to the grid. The physical design thus implemented is correct-by-construction and is free of violations of one or more directional design rules.

Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness

Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design by identifying rules for a first layer and for second layer(s) adjacent to the first layer, determining one or more sets of grids based on the rules, extending or implementing shapes to terminate at some grids of the one or more sets of grids, and populating the data of the ends of the shapes in the first layer in a data structure. The one or more sets of grids are in direction(s) perpendicular to the routing direction(s) of the first layer and have one or more grid pitches determined based at least in part upon routing pitch(es) of the second layer(s) and rule(s) for vias.

Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design

Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or coloring routing track(s). Some embodiments route the physical design with coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Multiple-patterning conflicts may be detected based on the coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Some embodiments route with search-and-repair strategy(ies) to improve or resolve conflict(s). Some embodiments color objects upon their creation, and the layout is thus multiple-patterning design rule clean as constructed.

Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques

A method and system for pattern-driven routing are disclosed. Embodiments of pattern-driven routing are disclosed for creating a representation for at least a portion of an initial routing solution, comparing the representation for at least the portion of the initial routing solution with a pattern, and determining whether the initial routing solution has lithographic issues based on the comparison.

Pattern-driven routing

Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Growing community of inventors

Los Gatos, CA, United States of America

Jianmin Li