Marvell Asia Pte., Ltd.

Marvell International Limited

Jianmin Guo

Hui Wang

Xin Ma

Wenjie Li

Jingjing Deng

Changguo Shen

Pilong Gao

Yonghua Song

Tao Shui

Hao Zhou

Yihui Li

Hong Xue

Aspects of the disclosure provide a receiver for receiving data over a wired communication channel. The receiver includes an analog front end circuit, a pulse generation circuit and a voltage-controlled oscillator (VCO). The analog front end circuit receives an analog signal carrying data over the wired communication channel, and outputs a data signal with data bit transitions between voltage levels. The pulse generation circuit generates a pulse signal in response to the data bit transitions in the data signal. The voltage-controlled oscillator (VCO) generates an oscillation signal for providing sampling clocks for the data signal. The voltage-controlled oscillator aligns transitions in the oscillation signal to the pulse signal by forcing the oscillation signal to transit voltage levels in response to a pulse in the pulse signal.

Method and apparatus for clock recovery

A short-reach data link receiver includes an edge detector configured to generate a pulse on an edge of a data input, a first clock-data recovery path coupled to an output of the edge detector for recovering a clock and data from the output of the edge detector, a second clock-data recovery path coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector, and a controller configured to alternate between the first and second clock-data recovery paths to recover the clock and data using one of the paths while calibrating the other path. The controller may swap the paths whenever calibration of one path is completed. That may include beginning calibration of the next path immediately after swapping of the paths. Alternatively, power consumption may be reduced by delaying calibration of the next path after swapping of the paths.

Oscillator calibration structure and method

A clock-data recovery circuit includes a variable data path delay, an injection-locked oscillator having a free-running frequency, and circuitry for adjusting at least one of the variable data path delay and the free-running frequency, including a counter configured to count repetitions of a bit value in an input data signal, and further being configured to, on occurrence of a first data pattern in the input data signal, indicative of saturation of inter-symbol interference, measure the input data signal at a first clock edge to determine a first data phase measurement value, measure the input data signal at clock centers immediately preceding and immediately following the first clock edge to determine second and third data phase measurement values, and based on first predetermined relationships among the first, second and third data phase measurement values, adjust the variable data path.

Phase and frequency control for clock-data recovery

A phase-locked loop (PLL) with a decreased frequency tuning gain Kand a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, K, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/&#x3b2; of that of the second voltage to current converter, wherein &#x3b2;&#x3e;1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is &#x3b1; times of the main charge pump, the capacitance of C1 may be reduced to just (1&#x2212;&#x3b1;) times of what it needed in a conventional loop stability compensation method, wherein &#x3b1;&#x3c;1.

Low-jitter phase-locked loop

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Sunnyvale, CA, United States of America

Jianmin Guo