Samsung Electronics Co., Ltd.

Nanjing Horizon Robotics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Tsinghua University

Huawei Technologies Co., Limited

Chengdu Boe Optoelectronics Technology Co., Ltd.

Seoul National University

Beijing Horizon Robotics Technology Research and Development Co., Ltd.

Other

Purdue Research Foundation

Ordos Yuansheng Optoelectronics Co., Ltd.

Nuctech Company Limited

Beijing Horizon Information Technology Co., Ltd

British Telecommunications Public Limited Company

Jianjun Li

Liang Chen

Sung-Jin Kim

Delin Li

Kun Ling

Ho-Jin Kim

Chang Huang

Yong-Xing Zhou

Jing Wang

Kwang-Bok Lee

Hwan-Joon Kwon

Zhiqiang Chen

Ju-Ho Lee

Yongxing Zhou

Chen Sun

Qiang Li

Yung-Soo Kim

Zheng Wang

Kejun Kang

Guang Yang

Shangmin Sun

Richard MacKenzie

Haifeng Hu

Kyung-Hun Jang

Hao Jiang

Zhenjiang Wang

Heng Luo

Chunlong Yan

Eung-sun Kim

Xin Xin Bai

Jiansong Gan

David James Love

Tianma Li

In-Soo Hwang

Fucheng Yang

Kun Hsien Lin

Yucheng Wu

Jung-Hoon Suh

Bin Ji

Zhigang Cao

Chang-soon Park

Jae-Kwon Kim

Mo Hao

Yuan Wu

Wenchu Han

Meng Yao

Yu Zhou

Arman Shojaeifard

Luxia Jiang

Il-Han Kim

Seung-Young Park

Jun Nie

Rongxuan Liu

Lixia Liu

Xuejiang Zhang

Jianguang Zhou

Long Zhen

Zecheng Li

Yong Bi

Fengjun Zhang

Shufu Mao

Haibo Zheng

Zhuoran Zhao

Linglong Dai

Haoqian He

Wenhui Cao

Heewoong Kim

Mingqian Hao

Guiqi Liu

Yijiong Zhang

Pinyi Fan

Disclosed is a method for convolution calculation in a neural network, comprising: reading an input feature map, depthwise convolution kernels and pointwise convolution kernels from a dynamic random access memory (DRAM); performing depthwise convolution calculations and pointwise convolution calculations by depthwise convolution calculation units and pointwise convolution calculation units, according to the input feature map, the depthwise convolution kernels and the pointwise convolution kernels to obtain output feature values of a first predetermined number p of points on all pointwise convolution output channels; storing the output feature values of a first predetermined number p of points on all pointwise convolution output channels into an on-chip memory; and repeating above operation to obtain output feature values of all points on all point wise convolution output channels. Therefore, the storage space for storing intermediate results may be reduced.

Method, electronic device and storage medium for convolution calculation in neural network

Systems and methods of data processing are provided. The method comprises receiving an input data to be processed by a series of operations, identifying a first operation from the series of operations, selecting at least one second operation from the series of operations to be grouped with the first operation based at least in part on an amount of an input data and an output data of the grouped operations and the capacity of the memory unit, and processing a portion of the input data of the grouped operations. An efficiency of the series of data operations can be improved by ensuring the input data and output data of any data operations are both stored in the memory unit.

Convolutional neural network operation grouping based on memory unit capacity

Disclosed are a convolution processing engine and a control method thereof, and a convolutional neural network accelerator comprising the convolution processing engine. The convolution processing engine comprises at least two cache memories connected in series and an operational circuit. The convolution processing engine can realize an efficient convolution operation with lower complexity and power consumption.

Convolution processing engine and control method, and corresponding convolutional neural network accelerator

Disclosed are a method and an apparatus for performing an operation of a convolutional layer in a convolutional neural network. The method comprises: reading unfolded feature data provided to the convolution layer and an original convolution kernel of the convolutional layer from a dynamic random access memory (DRAM); folding the unfolded feature data in at least one dimension of width and height to generate folded feature data; pre-processing the folded feature data and the original convolution kernel; storing the pre-processed folded feature data into a static random-access memory (SRAM); folding the pre-processed original convolution kernel in the at least one dimension to generate one or more folded convolution kernels corresponding to the original convolution kernel; storing the one or more folded convolution kernels in the SRAM; and reading the pre-processed folded feature data and the one or more folded convolution kernels from the SRAM into a calculation unit for convolving the pre-processed folded feature data with the one or more folded convolution kernels. By means of the method and/or apparatus in accordance with embodiments of the present disclosure, channel utilization may be improved, cache occupancy may be reduced, and operation efficiency may be improved.

Method and apparatus for performing operation of convolutional layers in convolutional neural network

This application discloses a data processing method and apparatus, an electronic device, and a storage medium. When execution is performed at an operation layer of a neural network model, based on a pre-stored buffer allocation relationship, a first address range for cyclic addressing is set for a first buffer corresponding to input data and a second address range for cyclic addressing is set for a second buffer corresponding to an output result. Subsequently, cyclic addressing can be performed in the first buffer based on the first address range for cyclic addressing, to read the input data for the operation layer; and cyclic addressing can be performed in the second buffer based on the second address range for cyclic addressing, to write the output result of the operation layer into the second buffer. In this way, efficiency of buffer utilization can be effectively improved, and further operation efficiency for the model is improved.

Method and electronic device for data processing, and storage medium

Disclosed are a data compression method, a computer-readable storage medium, and an electronic device. The method includes: converting each data in a to-be-compressed data set into binary data in a preset format; determining a to-be-compressed bit and a significant bit for the each data in the to-be-compressed data set based on a sequence of all bits of the binary data; determining a compression bit width corresponding to the to-be-compressed data set based on bit widths of the significant bits; compressing the each data in the to-be-compressed data set based on the compression bit width, to obtain a compressed data set; and generating attribute information of the compressed data set. According to the present disclosure, the significant bit can be determined based on the sequence of all bits without adjusting orders of the bits of the binary data, thereby simplifying a data compression process and improving efficiency of data compression.

Data compression method and apparatus, computer-readable storage medium, and electronic device

Disclosed is a method for convolution calculation in a neural network, comprising: reading an input feature map, depthwise convolution kernels and pointwise convolution kernels from a dynamitic random access memory (DRAM); performing depthwise convolution calculations and pointwise convolution calculations according to the input feature map, the depthwise convolution kernels and the pointwise convolution kernels to obtain output feature values of a first predetermined number p of points on all pointwise convolution output channels; storing the output feature values of a first predetermined number p of points on all pointwise convolution output channels into an on-chip memory, wherein the first predetermined number p is determined according to at least one of available space in the on-chip memory, a number of the depthwise convolution calculation units, and width, height and channel dimensions of the input feature map; and repeating the above operation obtain output feature values of all points on all pointwise convolution output channels. Therefore, the storage space for storing intermediate results may be reduced.

Method and electronic device for convolution calculation in neural network

A method and an apparatus for adapting feature data in a convolutional neural network. The method includes selecting a plurality of consecutive layers; determining an expected number of subdata blocks and a layout position, width and height of each subdata block in an output feature data of a last layer; determining, for each current layer, a layout position, width, and height of each subdata block of an input feature data for the current layer according to the layout position, width, and height of each subdata block of the output feature data for the current layer; determining an actual position of each subdata block of the input feature data for a first layer in the input feature data for the first layer; and obtaining the expected number of subdata blocks of the input feature data for the first layer according to the actual position, width and height of each subdata block of the input feature data for the first layer.

Method and apparatus for adapting feature data in a convolutional neural network

Disclosed are a method and an apparatus for performing convolution operation on folded feature data. The method comprises: reading the folded feature data provided to a convolution layer and an original convolution kernel from a dynamic random access memory (DRAM); pre-processing the folded feature data and the original convolution kernel; storing the pre-processed folded feature data into a static random-access memory (SRAM); folding the pre-processed original convolution kernel in at least one dimension of width or height according to a folding manner of the folded feature data to generate one or more folded convolution kernels corresponding to the original convolution kernel; storing the one or more folded convolution kernels in the SRAM; and reading the pre-processed folded feature data and the one or more folded convolution kernels from the SRAM into a calculation unit for convolving the pre-processed folded feature data with the one or more folded convolution kernels.

Method and apparatus for performing convolution operation on folded feature data

Disclosed are a method and an apparatus for performing an operation of a convolutional layer in a convolutional neural network. The method includes reading unfolded-feature-data and an original convolution kernel from DRAM, padding the unfolded-feature-data, folding the padded unfolded-feature-data in at least one dimension folded feature data, storing the folded feature data into a SRAM, folding the original convolution kernel in the at least one dimension to generate one or more folded convolution kernels, storing the one or more folded convolution kernels in the SRAM and reading the folded feature data and the one or more folded convolution kernels from the SRAM into a calculation circuit for performing a convolution operation on the folded feature data by using the one or more folded convolution kernels.

Method and apparatus for performing operation of convolutional layer in convolutional neural network

Disclosed are a method and an apparatus for adapting parameters of a neural network. The method includes selecting one or more dimensions for a weight parameter of each of at least one layer of the neural network, determining a dimension value and a corresponding target value in each dimension of the weight parameter, and padding the weight parameter in a case where the dimension value in at least one dimension of the weight parameter is less than the corresponding target value, the dimension value in each dimension of the weight parameter after the padding being equal to the corresponding target value.

Method and apparatus for adapting parameters of neural network

A chip programming voltage detection circuit and a chip programming voltage detection method are disclosed. The chip programming voltage detection circuit comprises a detection subcircuit and a warning subcircuit. The detection subcircuit detects a voltage at a programming voltage output pin, and outputs a detection signal based on the voltage at the programming voltage output pin. The warning subcircuit is connected to a detection output terminal of the detection subcircuit, and is operated to issue a warning alarm in a case where the detection signal indicates that the voltage at the programming voltage output pin does not reach a voltage required for an IC chip programming.

Chip programming voltage detection circuit and detection method

A method and apparatus are disclosed to perform the circular addressing to emulate a virtually unlimited memory space despite the fixed capacity of a physical memory by readdressing the portion of the data that exceeds the pre-defined length of the circular addressing region to another pre-defined address in the circular addressing region. Data segments in a data sample can be loaded and computed with recalculated circular addresses for different applications.

Methods and apparatus for using circular addressing in convolutional operation

The present disclosure provides a display substrate, including a base substrate, and a black matrix pattern and a color filter pattern on the base substrate. The black matrix pattern defines one or more display regions of the display substrate and a non-display region surrounding the one or more display regions. The color filter pattern includes a plurality of color filter sub-patterns, each color filter sub-pattern includes a plurality of color filter units, and each color filter unit includes a body portion. At least one of the color filter units further includes an anchoring portion extending from the body portion, and in a direction perpendicular to an extension direction of the body portion, the anchoring portion has a size greater than the body portion. The present disclosure further provides a method for manufacturing the display substrate, a display device and a mask.

Display substrate, manufacturing method thereof, display device and mask

A pixel array, including: a plurality of pixel groups, the pixel group including six sub-pixels arranged in a column direction, wherein a connecting line connecting central points of a first, a third and a fifth sub-pixels is on a first straight line, a connecting line connecting central points of a second, a fourth and a sixth sub-pixels is on a second straight line different from the first straight line, and the first straight line and the second straight line are parallel to the column direction; wherein successive connecting lines connecting central points of the six sub-pixels are in a zigzag form, and a connecting line connecting central points of any two adjacent sub-pixels in the column direction is not perpendicular to the first straight line; and wherein in the pixel group, colors of any three adjacent sub-pixels in the column direction are all different.

Pixel array, display panel, display device and driving method

Growing community of inventors

Beijing, China

Jianjun Li