Yangtze Memory Technologies Co., Ltd.

Jianjie Li

Weijun Wan

According to one aspect of the present disclosure, a method of controlling a memory is provided. The method may include performing a read operation based on a read voltage corresponding to a target logical page to obtain a hard read value and a soft read value of the target logical page. The method may include storing the hard read value, the soft read value, and inhibition information into three latches in a page buffer respectively. The method may include obtaining hard data of the target logical page based on the hard read value of the target logical page. The method may include obtaining soft data of the target logical page based on the hard data and the soft read value of the target logical page. The memory may include a plurality of memory cells, each configured to store N-bit data, where N is an integer greater than 1.

Method of controlling memory, memory and memory system

In an aspect, a memory device includes page buffers and a controller coupled to the page buffers. Each of the page buffers includes N data latches configured to store data, where N is a positive integer. The controller is configured to receive data that includes data units, wherein each of the data units includes N bits, store the data units in the N data latches, convert the data stored in the N data latches based on a table, and program cells of the memory device based on the converted data. The table include N rows and 2columns of bits. Bits from column 2+2 to column 2in Nrow of the table are identical.

Data preprocessing (DPP) pattern supporting both normal program and early cache release program (ECRP)

Disclosed herein are memory device, method for data preprocessing of program operations. In an aspect, a memory device comprises N data latches configured to store data and a controller coupled to the N data latches. The controller is configured to receive the data that includes data units and store the data units in the N data latches, wherein each of the data units includes N bits. The processor is further configured to convert the data units based on a first table and a second table and program cells of the memory device based on the converted data units. The first and the second tables include N rows and 2columns of bits and bits from column 2+2 to column 2in Nrow of the second table are identical.

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Wuhan, China

Jianjie Li