Intel Corporation

Jianhui Li

Yong Wu

Xueliang Zhong

Yihua Jin

Xiao Dong Lin

Yu Wang

Orna Etzion

Tingtao Li

Yun Yu Wang

Wen Tan

Xiaodong Lin

Jian Ye Chen

Miaobo Chen

Eric Lin

Peng Zhang

Bo Huang

Gang Wang

Zhiqiang Yu

Hui Chen

Jianping Chen

Shu Xu

Tianyou Li

Daniel M Lavery

Tao Xie

Ling Lin

Kevin James Jones

Yi Qian

Qian Qian

Alex Skaletsky

Yigal Zemach

Xianfeng Zhang

Honesty Young

Li Yin

Yuqiang Xian

Baiming Gao

Jian Ping Jane Chen

Huifeng Gu

Guokai Ma

Jinrong Gong

Honesty Cheng Young

Qi Zhang

An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

Efficient address translation

One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Nested emulation and dynamic linking environment

Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.

Seamless host system gesture experience for guest applications on touch based devices

An apparatus and method are described for improving the efficiency of graphics operations in a virtual execution environment. For example, one embodiment of a system comprises: a classification module to detect graphics application programming interface (API) calls in a guest execution environment and responsively classify the graphics API calls as originating from an application or a system component; the classification module to associate information with each of the graphics API calls to indicate whether each of the graphics API calls originated from the application or from the system component; and an enhanced graphics API translator (EGAT) to translate the graphics API calls to a format executable in a host execution environment, the EGAT to identify each of the API calls as originating from the application or the system component using the information associated with the graphics API calls by the classification module, the EGAT comprising: a first translation sequence to translate the graphics API calls to a first set of translated graphics API calls if the graphics API calls originated from the application; and a second translation sequence to translate the graphics API calls to a second set of translated graphics API calls if the graphics API calls originated from the system component, the first set of translated graphics API calls being different from the second set of translated graphics API calls.

Apparatus and method for efficient graphics processing in a virtual execution environment

Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

Methods and systems for performing a binary translation

Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

System and method for execution of application code compiled according to two instruction set architectures

Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Multiple processor modes execution method and apparatus including signal handling

Methods, apparatuses and storage medium associated with ISA bridging with callback, are disclosed. In various embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution of the instructions, to provide an ISA bridging layer to the target device to facilitate a library service to callback a callback function of an application. The library service may be implemented for the target ISA, and the application may be implemented at least partially for a source ISA that may be different from the target ISA. The ISA bridging layer may include a source ISA emulator and a library emulator configured to cooperate to enable the application to call the library service, and the library service to callback the callback function, across the two instruction set architectures. Other embodiments may be disclosed or claimed.

ISA bridging with callback

A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.

Method and apparatus to schedule store instructions across atomic regions in binary translation

An executable program compiled according to a source instruction set architecture (source ISA) is loaded for execution by a target instruction set architecture (target ISA)-based hardware execution unit, wherein the source and target ISA's are different. The loading includes mapping a compiler built-in helper function in the executable program to a target ISA machine instruction. The loaded program is then executed. As part of the execution, the helper function is replaced with the target ISA machine instruction to which the helper function was mapped, and the target ISA machine instruction is executed rather than the helper function.

Method and apparatus for substituting compiler built-in helper functions with machine instructions

Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.

ISA bridging including support for call to overidding virtual functions

Methods, systems, and articles for receiving, by a computing device, execution results of a plurality of query language expressions are described herein. In various embodiments, the plurality of query language expressions may be concurrently executed, and the receiving may be contemporaneous with production of the execution results. Also, in various embodiments, the computing device may store a result item of the execution results for at least a first of the query language expressions in a memory block allocated exclusively for the first of the query language expressions while the first of the query language expressions is being executed, or in a result handle associated with the first of the query language expressions.

Storage and retrieval of concurrent query language execution results

Methods and apparatuses for creating a dynamic profile for a plurality of structurally similar extensible markup language (XML) documents based at least in part on a document structure or data pattern of the XML documents. A specialized XML parser is generated based at least in part on the dynamic profile and then is specialized in parsing XML documents that substantially match the dynamic profile.

Growing community of inventors

Shanghai, China

Jianhui Li