Gowin Semiconductor Corporation

Other

Altera Corporation

Jianhua Liu

Jinghui Zhu

Ning Song

Chienkuang Chen

Diwakar Chopperla

Xiaozhi Lin

Zhenyu Gu

Tianping Wang

Tianxin Wang

Grant Thomas Jennings

Jiyong Zhang

Gregg William Baeckler

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

A programmable semiconductor device contains a wireless communication block ('WCB') capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

Method and system for providing wireless FPGA programming download via a wireless communication block

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.

System architecture based on SoC FPGA for edge artificial intelligence computing

A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (&#x201c;CSQ&#x201d;) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (&#x201c;NCSs&#x201d;) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (&#x201c;SCSs&#x201d;) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions

A programmable logic device ('PLD') contains programmable digital signal processing ('DSP') blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (&#x201c;LBs&#x201d;), an input and output (&#x201c;I/O&#x201d;) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27&#xd7;18 multiplier and a 12&#xd7;12 multiplier.

Method and system for providing a configurable logic device having a programmable DSP block

A programmable semiconductor device contains a wireless communication block ('WCB') capable of facilitating wirelessly field programmable gate array ('FPGA') programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (&#x201c;CDB&#x201d;) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (&#x201c;LBs&#x201d;) in FPGA in response to the configuration bitstream.

A process or method for facilitating configuring a field programmable gate array ('FPGA') using a group of configurable logic blocks ('CLBs') to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (&#x201c;DPR&#x201d;) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

Method and system for providing regional electrical grid for power conservation in a programmable device

A semiconductor device contains an integrated circuit ('IC') capable of being selectively programmed to perform one or more logic functions. The device, in one embodiment, includes multiple logic blocks ('LBs'), a routing fabric, and a configurable wireless communication block (&#x201c;WCB&#x201d;). The configurable LBs is able to be selectively programmed to perform one or more logic functions. The routing fabric is used to route information between the configurable LBs and input/output ports based on a routing configuration signals. The configurable WCB, having a control circuit and a built-in transceiver, is configured to facilitate transmitting information between the IC and an external system via a wireless communications network.

Method and system for providing a programmable logic device having a configurable wireless communication block field

A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control ('RPC'), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks ('CLBs') able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion of the bits of the pre-scaled fractional divisor. This value is used to scale the fractional operands and a multiply-add operation is used based on principles of series expansion to compute a final result with an acceptable degree of accuracy.

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Fremont, CA, United States of America

Jianhua Liu