Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Jianhua Ju

Shaofeng Yu

Qiang Wu

Chang Liu

Mieno Fumitake

Shuai Zhang

Huayong Hu

Charles Kwok Fung Lee

Fei Zhou

Yang Liu

Jun Yang

Xian Jay Ning

Xianjie Ning

Zhaoxu Shen

YongMeng Lee

A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Semiconductor device manufacturing method with reduced gate electrode height loss and related devices

A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.

Patterning method

A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation.

Transistor and fabrication method thereof

Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.

Fin field effect transistor

A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

Semiconductor structure and fabrication method thereof, and static random access memory cell

Patterning apparatus and patterning methods thereof

A method for forming a FinFET device is provided. The method includes providing a substrate having a first region and a second region; and forming a plurality of fins on the substrate. The method also includes forming a plurality of doping regions with different doping concentrations in the fins in the first region; and forming a plurality of dummy gate structures over the plurality of fins. Further, the method includes forming source and drain regions in the plurality of fins at both sides of the dummy gate structures; and removing the dummy gate structures to form a plurality of openings to expose the plurality of fins. Further, the method also includes forming a plurality of work function layers with different work functions on the exposed fins in the openings in the second region; and forming gate structures in the openings.

FinFET device and fabrication method thereof

A method of manufacturing a fin-type field effect transistor includes sequentially forming a first mask and a second mask on a semiconductor substrate; patterning the second mask; forming and patterning a third mask on the second mask in accordance with a fin pattern of the fin-type field effect transistor; etching the semiconductor substrate, the first mask, and the second mask through the third mask, wherein portions of the first and second masks are removed and a first trench is formed in the semiconductor substrate; removing the third mask; etching the first mask through the second mask and removing the second mask; etching the semiconductor substrate through the first mask to form a plurality of fins and a second trench disposed between adjacent fins, wherein etching the semiconductor substrate further deepens the first trench such that a depth of the first trench is greater than a depth of the second trench.

Fin-type field effect transistor and manufacturing method thereof

Fin field effect transistor and method for forming the same

A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors. The transistors include a pull-up transistor, a transfer gate transistor, and a pull-down transistor of a SRAM cell. The ion implantation is used to adjust threshold voltages of the transistors. Standard threshold voltage (SVt) ion implantation conditions are used to adjust a threshold voltage of the pull-up transistor and a threshold voltage of the transfer gate transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a threshold voltage of the pull-down transistor.

Method of manufacturing a semiconductor device and adjusting threshold voltages in the same

The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures.

Method for circuit layout and rapid thermal annealing method for semiconductor apparatus

The present invention discloses a rapid thermal annealing method for a semiconductor device, which includes the steps of: establishing a ternary correspondence relationship among a device electrical parameter, an annealing temperature, and an STI distribution density; deriving an STI distribution density in a specific area of the semiconductor device and a target STI distribution density; determining whether the STI distribution density in the specific area is larger than the target STI distribution density; if the STI distribution density in the specific area is larger than the target STI distribution density, adding a virtual structure in the specific area to make the STI distribution density in the specific area equal to the target STI distribution density; and deriving from the ternary correspondence relationship a target annealing temperature corresponding to the target STI distribution density and performing an annealing process with the annealing temperature on the semiconductor device to achieve a target electrical parameter. The method can alleviate the phenomenon of temperature non-uniformity of a rapid thermal annealing process so as to avoid any influence thereof upon the electrical performance of the semiconductor device.

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Shanghai, China

Jianhua Ju