Inspur Suzhou Intelligent Technology Co., Ltd

Suzhou Metabrain Intelligent Technology Co., Ltd.

Jiangwei Wang

Hongwei Kan

Rui Hao

Jingdong Zhang

Rengang Li

Yanwei Wang

Guoqiang Mei

Yuanli Wang

Dongdong Su

Le Yang

Kefeng Zhu

Lei Guo

Yaming Xu

Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Communication method and system for distributed heterogeneous acceleration platform, device and medium

A graph data processing method includes: acquiring target graph data to be processed; compiling statistics on the target graph data according to a first preset rule, so as to divide the target graph data into a plurality of graph data blocks and determine a boundary value and weight of each of the plurality of graph data blocks; and storing the boundary value and weight of each of the plurality of graph data blocks in a corresponding memory according to a second preset rule, so as to schedule the target graph data during a graph calculation process by use of the boundary values and the weights.

Graph data processing method, apparatus, and device, and medium

A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Far-end data migration device and method based on FPGA cloud platform

A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Method and apparatus for performing power stress test on FPGA acceleration card, and storage medium

Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

Avalon-to-Axi4 bus conversion method

Growing community of inventors

Jiangsu, China

Jiangwei Wang