Qualcomm Incorporated

National Semiconductor Corporation

Pixtronix, Incorporated

Jianguo Yao

Xia Li

Bin Yang

Matthew Louis Courcy

Seung Hyuk Kang

Roger W Barton

Stephen R Lewis

Helena Deirdre O'Shea

John Edward DeRoo

ZhenQi Chen

Stephen English

Min Chen

Scott Davenport

Reza Mohammadpourrad

Michael J Guidry, Jr

Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Static random-access memory (SRAM) compute in-memory integration

In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

Dynamic aging monitor and correction for critical path duty cycle and delay degradation

Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

On-chip clock generator calibration

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance are disclosed. Added passive resistance can enhance imbalance between transistors in the SRAM bit cell for improved PUF output reproducibility. Enhancing transistor imbalance can more fully skew the SRAM bit cell for increased PUF output reproducibility while still achieving the benefits of output randomness. In one exemplary aspect, added passive resistances in the SRAM bit cell are coupled to a drain of one or more pull-down N-type FETs (NFETs)) in one or more cross-coupled inverters in the SRAM bit cell to enhance imbalance between the inverters. Enhanced imbalance between the inverters increases sensitivity in the output voltage of the SRAM bit cell for a given change in input voltage resulting in greater skew of the SRAM bit cell for increased reproducibility.

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance to enhance transistor imbalance for improved PUF output reproducibility

Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.

Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption

A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.

Circuits for controlling display apparatus

This disclosure provides systems, methods and apparatus for improving the reliability of dual actuator light modulators by equalizing voltages provided to the two actuators of the light modulator. A pixel circuit for driving the dual actuator light modulator can include a data loading circuit coupled to an actuation circuit. The data loading circuit is utilized to store data received from a controller for a pixel associated with the light modulator. The actuation circuit is utilized to control a first actuator and a second actuator of the dual actuator light modulator based on the data stored by the data loading circuit. The actuation circuit includes a first stabilization capacitor and a second stabilization capacitor for stabilizing voltages provided to the first and second actuators. The actuation circuit also includes an equalization switch for equalizing voltages provided to the first and second actuators.

Display element pixel circuit with voltage equalization

An analog front end for a multi-channel signal processor is provided. The analog front end includes a first stage that is operable to receive a plurality of channel inputs. The first stage includes a ping/pong capacitor array corresponding to each of the channel inputs and an operational amplifier that may be coupled successively to each of the ping/pong capacitor arrays.

System and method for reducing power consumption in a multi-channel signal processor

An amplifier circuit includes a first amplifier and a second amplifier and sets of switching devices controlled by a bistate control signal. The bistate control signal is in the first state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a positive parallel configuration and the bistate control signal is in the second state to cause the first and second sets of switching devices to configure the first amplifier and the second amplifier in a negative parallel configuration. When the bistate control signal switches states at each sample cycle of the amplifier circuit, the first amplifier and the second amplifier toggle between the positive parallel configuration and the negative parallel configurations to cancel out crosstalk signals stored at the positive and negative input terminals of the first and second amplifier circuit.

Split amplifier architecture for cross talk cancellation

A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.

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Londonderry, NH, United States of America

Jianguo Yao