Smarter Microelectronics (shanghai) Co., Ltd.

Jiangtao Yi

Jun Ma

Lei Zhang

Qiang Su

Xin Wang

Baiming Xu

Xue Yang

A radio frequency amplification processing circuit includes: a radio frequency power amplifier, a transmitting antenna and a filter element; the radio frequency power amplifier is configured to perform radio frequency amplification on a modulated first wireless communication signal, and transmit, with a first line, the amplified first wireless communication signal to the transmitting antenna for transmission, or perform radio frequency amplification on a modulated second wireless communication signal, and transmit, with a second line, the amplified second wireless communication signal to the filter element; and the filter element is configured to filter the amplified second wireless communication signal, and transmit, also with the second line, the filtered second wireless communication signal to the transmitting antenna for transmission.

Radio frequency amplification processing circuit and communication terminal

A control circuit can be applied to a bias circuit including a first transistor and a second transistor with their gates connected. The first and second transistors are configured to amplify an input reference direct current (DC) current of the bias circuit to obtain a bias DC current. The control circuit includes: a detection circuit configured to compare a first DC voltage with a second DC voltage to obtain a comparison result; the first DC voltage being a drain DC voltage of the first transistor; and the second DC voltage being a drain DC voltage of the second transistor; and an adjustment circuit configured to adjust the first DC voltage and the second DC voltage by using the comparison result, such that the drain DC voltage of the first transistor equals the drain DC voltage of the second transistor when the bias circuit is in operation.

Control circuit, bias circuit, and control method

A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time.

Growing community of inventors

Shanghai, China

Jiangtao Yi