Oracle International Corporation

Oracle America, Inc.

Velodyne Lidar Usa, Inc.

Jianghui Su

Dawei Huang

Xun Zhang

Deqiang Song

Muthukumar Vairavan

Chaitanya Palusa

Yan Yan

Hongtao Zhang

Drew George Doblar

Rajesh Kumar

Pravin Kumar Venkatesan

Zuxu Qin

Roger Pinto

Abhilash Goyal

Baoqing Huang

Osman Javed

Jiangyuan Li

Ranjan Vaish

Jieda Li

Ali Gokhan Ileri

Sifang You

Jihong Min

Pu Chuang

Da-wei Huang

Francis Schumacher

Yuhan Yao

Quang H Trang

Described herein are systems and methods that detect an electromagnetic signal in a constant interference environment. In one embodiment, the electromagnetic signal is a light signal. A constant interference detector may detect false signal 'hits' generated by constant interference, such as bright light saturation, from valid signals. The constant interference detector determines if there is constant interference for a time period that is greater than a time period of the valid signal. In one embodiment, if a received signal exceeds a programmable threshold value for a programmable period of time, when compared to previously stored ambient light, a control signal is generated to inform the next higher network layer of a sudden change in ambient light. This control signal can be used to either discard the present return or process the signal in a different way. A constant interference detector may be a component of a LIDAR system.

Systems and methods for detecting an electromagnetic signal in a constant interference environment

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Adaptive receiver with pre-cursor cancelation

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

Adapative receiver with pre-cursor cancelation

A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.

Baseline wander correction using zero and one mismatch adaptation

Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.

Baud-rate clock data recovery with improved tracking performance

Embodiments include systems and methods for implementing a multi-rate FIR by using rate-dependent bit stuffing on the cursor, while using rate-independent (e.g., full-rate) spacing on the pre- and post-cursor. For example, in the FIR data path, the cursor bit output is generated using bit stuffing, depending on a selected rate mode (e.g., full-rate, half-rate, quarter-rate, eighth-rate, etc.), but the spacing of the pre-cursor, cursor, and post-cursor are maintained at 1 UI apart (i.e., the full-rate spacing) for all rate modes. Such an approach can appreciably reduce complexity of the logic and can appreciably relieve the critical timing path.

Multi-rate finite impulse response filter

Embodiments include systems and methods for baseline wander correction gain adaptation in receiver circuits. Some embodiments operate in context of an alternating current coupled transceiver communicating data signals over a high-speed transmission channel, such that the receiver system includes an AC-coupled data input and a feedback loop with a data slicer and an error slicer. A baseline wander correction (BWC) circuit can be part of the feedback loop and can generate a feedback signal corresponding to low-pass-filtered bits data from the data slicer output and having a gain generated according to pattern-filtered error data from the error slicer output. For example, gain adaptation is performed according to error information corresponding to a detected relatively high-frequency data pattern following a long low-frequency pattern.

Baseline wander correction gain adaptation

Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(&#x2212;1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

At-rate SERDES clock data recovery with controllable offset

Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn&#x2212;1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).

Fast direct feedback circuit for decision feedback equalization correction

An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Method for duty cycle distortion detection through decision feedback equalizer taps

Embodiments include systems and methods for increasing frequency offset tracking in clock data recovery (CDR) systems. For example, in asynchronous clocking environments, the receiver-side clock frequency can be offset from the transmitter-side clock. While traditional CDR systems can handle some amount of offset, they are typically ineffective at accurately adapting the receiver-side clocking to an optimal data sampling rate when the offset is excessive. Embodiments include a CDR frequency offset adaptation loop that generates an adaptation signal, which can be monitored to detect an adaptation error arising from excessive frequency offset. In response to the detecting, an offset seed can be selected and injected into the frequency offset adaptation loop, thereby reinitializing the frequency offset adaptation loop with a less stressful seed.

Clock data recovery with increased frequency offset tracking

Embodiments include systems and methods for using generalized pulse amplitude modulation (PAM-X) signaling with an at-rate not-return-to-zero (NRZ) clock data recovery (CDR) system. Some implementations include dual-mode signaling for an at-rate CDR (e.g., using standard NRZ signaling at lower operating frequencies and pseudo-NRZ signaling derived from PAM-X signaling at higher operating frequencies. Embodiments derive an apparent direction of signal transition from PAM-X signaling. The direction can be used to calculate pseudo-NRZ values. For example, when the PAM-X signal transitions in an upward direction, a pseudo-current NRZ value and a pseudo-previous NRZ value of '&#x2212;1' and '+1' can be generated, respectively. An at-rate NRZ CDR can use the pseudo-NRZ values and a derived error value to make an offset determination. The offset determination can then be used to offset a generated clock signal in the CDR system.

Growing community of inventors

San Jose, CA, United States of America

Jianghui Su