Broadcom Corporation

Jiangfeng Wu

Tianwei Li

Donald Edward Major

Chun-Ying Chen

Ramon Alejandro Gomez

Wei-Te Chou

Wenbo Liu

David Garrett

Kevin Lee Miller

Lin He

Randall Bret Perlow

Frank Van Der Goes

Massimo Brandolini

Arnoldus Venes

Binning Chen

Rong Wu

Tao Wang

Wei-Ta Shih

Hans Eberhart

In some aspects, the disclosure is directed to methods and systems of a multi-input receiver. In one or more embodiments, a receiver receives a plurality of signals each via a respective one of a plurality of wireless channels. In one or more embodiments, a processing stage of the receiver combines the received plurality of signals into a combined signal for input to an analog-to-digital converter (ADC) of the receiver. In one or more embodiments, the ADC generates, at a predetermined sampling frequency, samples of the combined signal. In one or more embodiments, the receiver recovers from the generated samples at least one signal component corresponding to at least one of the plurality of signals.

Multi-input wireless receiver based on RF sampling techniques

Methods, systems, and apparatuses, including electrical circuits, are described for spread spectrum ADC noise reduction. An analog-to-digital converter may include an analog modulator to modulate an input analog signal according to a pseudo-noise sequence. An ADC core may convert the modulated analog input signal to a digital signal representation thereof. The digital signal may be demodulated using the pseudo-noise sequence to generate a noise-spread signal with reduced noise spectral density. The analog modulator and digital demodulator may also be configured in an analog-to-digital converter that includes a comparator and successive approximation register (SAR) logic, rather than an ADC core, in a SAR implementation. Multi-lane, interleaved analog-to-digital conversion circuits are also described using the inventive techniques. Analog-to-digital converters including DC offset components and methods performed according to the inventive techniques are also described.

System and method for spread spectrum ADC noise reduction

An Analog to Digital Converter (ADC) includes an ADC core, a first switched capacitor voltage regulator, and a second switched capacitor voltage regulator. The ADC core includes a plurality of digital components that sample an incoming signal based on an ADC clock, a first voltage, and a first ground and a plurality of analog components configured to operate using a second voltage and a second ground. The first switched capacitor voltage regulator produces the first voltage and the first ground for the plurality of digital components using a supply voltage, a supply ground, and the ADC clock. The second switched capacitor voltage regulator produces the second voltage and the second ground using the supply voltage, the supply ground, and the ADC clock. Switching of the first and second switched capacitor voltage regulators is performed using complementary and non-overlapping clocks having switching frequency that is based upon the ADC clock.

Analog to digital converter having switched capacitor power supply

An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N&#x2212;2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N&#x2212;2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

Interleaved multiple-stage capacitor and amplifier sharing in an ADC

Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fall. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

High efficiency output stage amplification for radio frequency (RF) transmitters

A method for digitizing an analog signal through a pipelined analog-to-digital converter (ADC) may include pipelining a sample sub-stage, a quantization sub-stage and an amplification sub-stage to an ADC lane. Within a first of multiple pipelined stages, clock phases may be assigned to the ADC lane, including a sample clock phase, a quantization clock phase, and an amplification clock phase such that the quantization clock phase is non-overlapping with the sample clock phase and the amplification clock phase. The non-overlapping feature may be facilitated by generating multiple reference clock phases for the sub-stages of multiple ADC lanes, and interleaving assignment of the sample clock phase, the quantization clock phase, and the amplification clock phase to the reference clock phases among the multiple lanes.

Pipelined analog-to-digital converter with dedicated clock cycle for quantization

Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

Successive equalizer for analog-to-digital converter (ADC) error correction

The present disclosure is directed to a switched capacitor amplifier that includes a switched capacitor network and a complementary push-pull amplifier. The switched capacitor amplifier of the present disclosure can provide a larger fraction of the charge provided by a power supply and flowing through the amplifier to a capacitive load at the output of the amplifier compared to switched capacitor amplifiers that use single-ended class-A amplifiers. The switched capacitor amplifier of the present disclosure can be used in a converter stage of a pipelined analog-to-digital converter (ADC) to improve the ADC's power efficiency and/or bandwidth. It can be further generalized to be used in other applications other than pipelined ADCs.

Complementary switched capacitor amplifier for pipelined ADCs and other applications

According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.

System including adaptive power rails and related method

A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Multi-protocol RF transceiver

A line driver comprises a driving amplifier receiving an input of the line driver, a current sense resistor connected between the driving amplifier output and the line driver output, and a feedback amplifier sensing the voltage across the current sense resistor and providing a corresponding feedback voltage that is proportional to the output current to the driving amplifier, thereby determining an output impedance at the line driver output. Precise output impedance can be realized by using a high precision resistor as the current sense resistor, and using resistive feedback amplifiers with accurate gains as the driving and feedback amplifiers. The resistance of the current sense resistor can be substantially less than the line driver output impedance, and the driving amplifier output voltage swing can be substantially less than twice the line driver output voltage swing.

Growing community of inventors

Irvine, CA, United States of America

Jiangfeng Wu