International Business Machines Corporation

Chengdu Haiguang Integrated Circuit Design Co., Ltd.

Samsung Electronics Co., Ltd.

Jiang Lin

Lixin Zhang

Chunhui Zhang

Leigang Kou

Matthew Derrick Garrett

Zehan Cui

Ruchir Dalal

Jing Li

Feng Zeng

A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

Cache management method, cache controller, processor and storage medium

This disclosure provides a method for tagging control information associated with a physical address in a processing system, including setting a hardware tag for the control information, the hardware tag being invisible to a software system in the processing system; joining the hardware tag with the physical address to form a compound physical address, the hardware tag including M bits carried by a dedicated hardware tag control line, the physical address including N bits carried by a physical address bus, M and N being positive integers; and tagging the control information with the hardware tag in the compound physical address.

Method for tagging control information associated with a physical address, processing system and device

Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.

Handling maximum activation count limit and target row refresh in DDR4 SDRAM

A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.

Cache partitioning with a partition table to effect allocation of ways and rows of the cache to virtual machine in virtualized environments

Cache partitioning with a partition table to effect allocation of shared cache to virtual machines in virtualized environments

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Austin, TX, United States of America

Jiang Lin