Huawei Technologies Co., Limited

Jianfu Zhong

Qi Chen

Yu Xia

Qiuling Zeng

A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS.

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Shenzhen, China

Jianfu Zhong