Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Tsinghua University

Jianbin Wang

Mengchen Yang

Xin Gao

Penghao Zou

Xiaoyuan Yu

Yu Zhang

Hongwei Wang

Weili Li

Junjie Zhang

Qianli Di

Xin-Yu Gao

Meng Tian

Meng-Chen Yang

Chenchen Song

Chen-Chen Song

Junlong Yin

Kang-Kang Zhang

Jing Qiao

The present invention provides a degradable microbead comprising a polymer molecule crosslinked by a crosslinking agent, wherein the polymer molecule and/or the crosslinking agent comprises a sensitive chemical bond that is cleavable through a chemical and/or light treatment, thereby resulting in the degradation of the degradable microbead. The present invention also provides a method of separating a target protein from a sample. By using the degradation of the degradable microbead to replace an elution step in protein purification, it is possible to select a combination of target protein and affinity ligand with a stronger affinity, thereby improving the protein purification efficiency. The method is especially suitable for the high-throughput preparation of multiple protein samples, for example providing a protein sample for electron microscope observation or mass spectrometry measurement.

Degradable microsphere and use thereof

A processor and an operating method thereof for renaming a destination logical register of a move instruction are provided. The processor comprises a plurality of physical registers and a renaming circuit. The renaming circuit is coupled to the plurality of physical registers and is configured to receive an instruction sequence and check the instruction sequence. When a current instruction of the instruction sequence comprises the move instruction, the renaming circuit assigns a first physical register, which is assigned to a source logical register of the current instruction previously, to the destination logical register of the current instruction. The first physical register is one of the plurality of physical registers.

Processor and operating method thereof for renaming destination logical register of move instruction

A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.

Cache memory device and data cache method

An instruction execution method suitable for being executed by a processor is provided. The first processor comprises a register alias table (RAT) and a reservation station. The instruction execution method includes: a register alias table receives a first micro-instruction and a second micro-instruction and issues the first micro-instruction and the second micro-instruction to the reservation station; and the reservation station assigns one of a plurality of execution units to execute the first micro-instruction, according to the first specific message of the first micro-instruction; and the reservation station assigns one of the execution units to execute the second micro-instruction, according to the second specific message of the second micro-instruction. When the reservation station determines that the execution units assigned for the first micro-instruction and the second micro-instruction are the same, the reservation station indicates that the second micro-instruction depends on the first micro-instruction.

Instruction execution method and instruction execution device

A parallelized multiple dispatch ordered queue including an ordered queue, qualify logic, ordered select logic, and dispatch logic. The ordered queue stores candidates in order from oldest to youngest into multiple entries. The ordered queue is divided into N groups in which an i'th group includes every i'th entry of every N entries of the ordered queue, wherein i is an integer less than or equal to N. The qualify logic determines whether any candidate is ready to be dispatched. The ordered select logic respectively determines the oldest candidate in each group that is ready to be dispatched. The dispatch logic dispatches the oldest ready candidates in parallel. The shift logic shifts the stored candidates in the ordered queue to fill any vacant entries between remaining ones of the stored candidates without changing an order of the remaining ones of the stored candidates in the ordered queue. The ordered queue may have any size or depth and N is any suitable integer determining the number of candidates (e.g., instructions) that may be dispatched in parallel.

Parallelized multiple dispatch system and method for ordered queue arbitration

A reissue instruction parking system for a microprocessor including a reservation stations module that dispatches instructions for execution and a reorder buffer that reissues instructions to the reservation stations module during a reissue state, in which the reissue instruction parking system includes at least one first pipeline stage and at least one second pipeline stage, in which the first pipeline stages provide a first reissue instruction from a reissue data path to the reservation stations module during the reissue state and that parks the first reissue instruction once the reservation stations module is determined to be full, and in which the second pipeline stages select a pointer to the reorder buffer which provides a corresponding first reissue instruction onto the reissue data path, in which the second pipeline stages are placed into a hold state when a second full signal is asserted.

System and method of reissue parking for a microprocessor

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Beijing, China

Jianbin Wang