Texas Instruments Corporation

Apple Inc.

Jianbao Wang

Nathan F Hanagami

Ruopeng Wang

Hao Zhou

Floyd L Dankert

Enrico Zanetti

Kiranjit Dhaliwal

Ludmil N Nikolov

Maryam Mortazavi

Systems and methods described herein correspond to supply harvesting operations. Power management circuitry may receive a supply voltage from other power management circuitry. This supply voltage may be a harvested supply from the other power management circuitry. Moreover, some of the power management circuitry may be operated as controller power management circuitry to supply the supply voltage via one or more rails and some of the power management circuitry may be operated as leaf power management circuitry to harvest the supply voltage from the one or more rails. Leaf power management circuitry may exclude a regulator, enabling that leaf power management circuitry to be entered into a lower power mode than previously enabled when the regulator was included.

General purpose input/output (GPIO) supply harvesting

A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.

Level shifter circuit with intermediate power domain

Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN). A ripple voltage (V) present on the input voltage causes a ripple current (I) through parasitic gate-drain capacitance of the pass transistor. A small ripple current (I) proportional to the ripple current (I) is generated and amplified to generate a cancellation current (I). The cancellation current is drawn from the gate of NMOS pass transistor (MN) to cancel the ripple current so that no net ripple current flows through the finite output impedance of an error amplifier (), to thereby achieve the PSRR improvement.

NMOS LDO PSRR improvement using power supply noise cancellation

A low drop out (LDO) voltage regulator () includes a pass transistor (MP) having a source coupled by an output conductor () to a load and a drain coupled to an input voltage to be regulated. An error amplifier () has a first input coupled to a reference voltage, a second input connected to a feedback conductor (A), and an output coupled to a gate of the pass transistor. A parallel path transistor (MP) has a source coupled to the input voltage, a gate coupled to the output () of the error amplifier (), and a drain coupled to the feedback conductor. A feedback resistor (R) is coupled between the feedback conductor and the output conductor.

Compensation of LDO regulator using parallel signal path with fractional frequency response

An LDO (low dropout) regulator including a pass transistor having a first electrode coupled to produce an output voltage of the LDO regulator, a control electrode, and a second electrode coupled to receive an input voltage of the LDO regulator. An error amplifier has a first input coupled to a first reference voltage and an output coupled to the gate control electrode of the pass transistor. A first feedback circuit has an input coupled to the first electrode of the pass transistor and an output producing a first feedback voltage coupled to a second input of the error amplifier. The auxiliary amplifier has a first input coupled to a second reference voltage and an output coupled to the output of the error amplifier. A second feedback circuit has an input coupled to the output of the auxiliary amplifier and an output producing a second feedback voltage coupled to a second input of the auxiliary amplifier. The auxiliary feedback loop is used to take over control of the feedback in the LDO regulator at high frequencies.

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Tucson, AZ, United States of America

Jianbao Wang