Freescale Semiconductor,inc.

Nxp Usa, Inc.

Other

Semiconductor Components Industries, LLC

Jianan Yang

Thomas W Liston

Brad John Garni

Mark W Jetton

James David Burnett

Stephen G Jamison

Shayan Zhang

Ravindraraj Ramaraju

Andrew Christopher Russell

George P Hoekstra

Gary R Morrison

Scott Ives Remington

David Wade Eickbusch

Wang K Chen

Huy Van Pham

David L Medlock

James Nissen

Gary Waugh

Darrin L Hutchinson

Level-shifting circuits including a plurality of p-type metal oxide semiconductor (PMOS) devices and n-type metal oxide semiconductor (NMOS) devices may be used to level-shift an input voltage signal between a low voltage domain having a low voltage level and a high voltage domain having a high voltage level, to obtain an output voltage signal having an output voltage level at an output node. A current-controlled tie circuit may be connected between the output node and the output voltage level, to conduct a current that causes the output node of the level-shifting circuit to be in a pre-defined logic state during a power-up sequence of the level-shifting circuit. Accordingly, spurious, non-deterministic output levels are avoided during the power-up sequence.

Level shifter with deterministic output during power-up sequence

A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.

Memory array with read only cells having multiple states and method of programming thereof

Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

Adaptable sense circuitry and method for read-only memory

A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.

Memory array with RAM and embedded ROM

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

Memory column drowsy control

A semiconductor device includes a parasitic silicon-controlled rectifier (SCR) and a first transistor. The parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The first transistor is coupled between a first power supply node and an emitter of the parasitic pnp BJT. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp BJT following a single-event latch-up (SEL) event.

Semiconductor device with single-event latch-up prevention circuitry

In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

Memory with word level power gating

An integrated circuit includes first and second memory cells including a first pull-up transistor each having a body tie coupled to respective first and second well bias voltages. Drain electrodes of the first and second pull-up transistors are coupled to a first true bit line and a first complementary bit line, respectively. A second memory cell includes first and second pull-up transistors each having a body tie coupled to the second and first well bias voltages, respectively. Drain electrodes of the first and second pull-up transistors are coupled to a second true bit line and a second complementary bit line, respectively. The first well bias voltage is lower than the second well bias voltage during a Read-Only Memory (ROM) mode, and the first well bias voltage is the same as the second well bias voltage during a Static Random Access Memory (SRAM) mode.

SRAM with embedded ROM

A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.

Method and apparatus for sensing on-chip characteristics

A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Single event latch-up prevention techniques for a semiconductor device

A flip-flop circuit includes a master latch, a master/slave gate, a slave latch, a slave gate, a feedback latch, and a master gate. The master latch has an input and an output. The master/slave gate has an input coupled to the output of the master latch and an output. The slave latch has input coupled to the output of the master/slave gate and an output. The slave gate has input coupled to the output of the slave latch and an output. The has an input coupled to the output of the slave gate and an output. The master gate has an input coupled to the output of the feedback latch and an output coupled to the input of the master latch.

Multi-threading flip-flop circuit

An integrated circuit comprises logic circuitry having a plurality of signal paths. A signal path of the plurality of signal paths has a propagation delay greater than a propagation delay of any other signal path of the plurality of signal paths. The signal path includes a plurality of components. The plurality of components is provided with a higher power supply voltage than any other signal path of the plurality of signal paths.

Integrated circuit having critical path voltage scaling and method therefor

An integrated circuit ECO base cell module is formed with PMOS and NMOS gate electrode structures and power supply lines that are electrically separated from one another up to the second metal (M) layer in a fixed circuit structure that may be reconfigured with one or more conductor elements formed above the Mlayer to form a predetermined circuit function.

Reconfigurable engineering change order base cell

First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.

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Austin, TX, United States of America

Jianan Yang