Shanghai Bright Power Semiconductor Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Schneider Electric Industries Sas

Innogrit Technologies Co., Ltd.

Bwi (shanghai) Co., Ltd.

Jian Wu

Lei Shi

Peng Wang

Yu-Lung Yeh

Chien-Chang Huang

Shih-Shiung Chen

Ming-Chi Wu

David Fredrick Reuter, Ii

Bin Chen

Ning Wang

Chi-Yuan Wen

Daniel Norbert Borgemenke

Chun-Chieh Fang

Hang Fan

Dongqiang Luo

Zhenzhong Liu

Wei-Tung Huang

Bin Zhou

Yu Zhao

Zhonghua Sun

Pascal Chaumette

Xiaojing Zeng

Shuming Xu

Shunxian Mao

Gang Yu

Shunfa Zhang

Luyao Song

Patrick N Hopkins

Dishi Lai

Jung-Yu Cheng

A semiconductor structure includes at least a first chip, the first chip comprising a semiconductor substrate and an active layer formed on an upper surface of the substrate, one or more lateral metal-oxide semiconductor devices being formed in the active layer of the first chip. The semiconductor structure further includes at least a first integrated capacitor disposed on a back-side of the semiconductor substrate of the first chip. The first integrated capacitor includes a first conductive layer in electrical connection with the back-side of the substrate, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.

Three-dimensional bipolar-CMOS-DMOS (BCD) structure with integrated back-side capacitor

A capacitor is provided for integration with a MOSFET device(s) formed on the same substrate. The capacitor comprises a first plate including a doped semiconductor layer of a first conductivity type, an insulating layer formed on an upper surface of the doped semiconductor layer, and a second plate including a polysilicon layer formed on an upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor. At least one doped region of a second conductivity type, opposite the first conductivity type, is formed in the doped semiconductor layer adjacent to a drain and/or source region of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.

Enhanced capacitor for integration with metal-oxide semiconductor field-effect transistor

An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

LDMOS device having isolation regions comprising DTI regions extending from a bottom of STI region

An interface control circuit, a control method and an interface control device. The interface control circuit is suitable for use in a dimming system compatible with both DALI dimming and push-button dimming. The interface control circuit includes a DALI signal reception control module having a first switch element. The DALI signal reception control module is configured to be enabled, upon a voltage at a power supply terminal of the interface control circuit reaching a pre-start voltage, to turn on or off the first switch element according to the magnitude of a voltage on a DALI bus. The pre-start voltage is lower than a start voltage of the interface control circuit. This invention can ensure accuracy and reliability of rapid communication reestablishment over a period of time from a power-off to the next power-on of the DALI bus.

Interface control circuit, control method and interface control device

This application discloses a method and system of using HMB as a cache of physical address mapping table. The method comprises: arranging physical addresses in order of logical addresses, physical mapping entries corresponding to a plurality of consecutive physical addresses form one table unit, and a logical address corresponding to a first entry of each table unit is used as an index of the table unit; determining HMB size, dividing all table units into a plurality of sections according to the HMB size, each section comprises a plurality of table units, each section is divided into a plurality of ways; calculating a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number; writing the metadata and the table unit to be stored into the HMB. This application uses HMB as L2P address mapping table cache of SSD controller, saving or avoiding use cost of DRAM on SSD, and reducing SSD size.

Method and system of using HMB as a cache of physical address mapping table

Disclosed are an electromagnet driving mechanism, an electromagnet driving assembly and a dual power automatic transfer switch. The electromagnet driving mechanism includes: a mechanism frame; a stationary core; a movable core, including a moving stroke between a first position away from the stationary core and a second position in contact with the stationary core, the moving stroke including an approaching stroke section; a coil, configured to generate a magnetic attraction force between the stationary core and the movable core upon being energized to drive the movable core to move towards the second position; a reset spring member; and a reset auxiliary assembly, including a push member and a reset auxiliary spring. The reset auxiliary assembly applies a reset auxiliary spring force to the movable core in the approaching stroke section through the push member.

Electromagnet driving mechanism, assembly and dual power automatic transfer switch

An electro-hydraulic brake assembly comprises a hydraulic control unit (HCU) body having a top surface and a bottom surface opposite the top surface and defining a master cylinder bore and a pressure supply bore. A fluid reservoir is disposed on the top surface. A primary piston is slidably disposed in the master cylinder bore and configured to supply brake fluid to a wheel brake in response to pressing of a brake pedal. A pressure supply unit includes: a pressure supply piston disposed within the pressure supply bore; a motor located on the bottom surface of the HCU body and having a motor shaft. An actuator mechanism includes a threaded shaft configured to be rotated by the motor shaft, and a nut coupled to the pressure supply piston, together causing the pressure supply piston to translate linearly through the pressure supply bore in response to rotation of the motor shaft.

Electro-hydraulic brake assembly

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Shanghai, China

Jian Wu