Neuchips Corporation

Elite Semiconductor Memory Technology, Inc

Advanced Semiconductor Engineering, Inc.

Novatek Microelectronics Corp.

Jian-Wen Chen

Youn-Long Lin

Chiung-Liang Lin

Chin-Yang Chen

Chih-wei Chang

Sung-Fei Wang

Po-Chin Hu

Chao-Yang Kao

Huang-Chih Kuo

Xiaoming Bu

YuShan Ruan

A matrix multiplier and an operation method thereof are provided. The matrix multiplier includes a plurality of first input lines, a plurality of second input lines and a computing array. The computing array includes a plurality of multiplication accumulation (MAC) cells. A first MAC cell of the plurality of MAC cells is coupled to a first corresponding input line of the plurality of first input lines and a second corresponding input line of the plurality of second input lines to receive a first input value and a second input value to perform a multiplication accumulation operation. When at least one of the first input value and the second input value is a specified value, the multiplication accumulation operation of the first MAC cell is disabled.

Matrix multiplier and operation method thereof

A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes a plurality of unit circuits. Each of the unit circuits includes a multiplying-adding circuit, a first register, and a second register. A first input terminal and a second input terminal of the multiplying-adding circuit are respectively coupled to a corresponding first input line and a corresponding second input line. An input terminal and an output terminal of the first register are respectively coupled to an output terminal and a third input terminal of the multiplying-adding circuit. The second register is coupled to the first register to receive and temporarily store a multiplication accumulation result. Wherein, the second registers of the unit circuits output the multiplication accumulation results in a column direction in a first output mode, and output the multiplication accumulation results in a row direction in a second output mode.

Matrix multiplication device and operation method thereof

A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes calculation circuits, a control circuit, a multiplication circuit, and a routing circuit. The calculation circuits produce multiply-accumulate values. The control circuit receives a plurality of first element values of a first matrix. The control circuit classifies the first element values into at least one classification value. The multiplication circuit multiplies the classification value by a second element value of a second matrix in a low power mode to obtain at least one product value. The routing circuit transmits each of the product values to at least one corresponding calculation circuit in the calculation circuits in the low power mode.

The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

Method of fixed-rate line-based embedded video compression and image processing apparatus using the same

A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.

Slew rate control circuit and method thereof and slew rate control device

A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.

Triangle wave generator and spread spectrum control circuit thereof

A stacked chip scale package. The stacked chip scale package has a substrate having mounting pads arranged to lie close to the rectangular sides. A smaller silicon chip is stacked on the active surface of a larger silicon chip and the larger silicon chip rest on the substrate. The mounting pads on the substrate are distributed around the periphery of the lower silicon chip. Both the upper silicon chip and the lower silicon chip have only one pair of opposite sides having bonding pads. The pair of edges of the upper silicon chip with bonding pads nearby is parallel to the pair of edges of the lower silicon chip without bonding pads. The bonding pads on the upper chip and the lower chip are electrically connected to their neighboring mounting pads through conductive wires. The conductive wires, the upper silicon chip, the lower silicon chip and a portion of the substrate are enclosed by packaging material.

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Hsinchu, Taiwan

Jian-Wen Chen