Qualcomm Incorporated

Greater Shine Limited

Jian Wei

Ying Hai Chen

Ning Bi

Richard Higgins

Inyup Kang

Gilbert Christopher Sih

Guofang Jiao

James M Brown

Tao Li

De Dzwo Hsu

Bruce R Meagher

Charles E Sakamaki

Chehui Wu

Lei Wang

Shimman Arvind Patel

Chun Yu

Christopher Patrick

David Chaohua Wu

Joseph Cheung

Jianfeng Ren

Kai Wang

Toshiaki Yoshino

Xuerui Zhang

Julio Arceo

Pillappakkam Bahukutumbi Srinivas

Yunke Pan

Srinivas Varadarajan

Gregory Foerster

Moto Oishi

Jalal Husseini

Brian Rodrigues

An architecture in which the cores of a multicore processor are paired together. An internal memory may be connected to the pair of cores via separate leads. The pair of cores can run at reversed clock phases. A clock generator may be responsible for generating a clock signal that can be provided as input to one core, and a signal inverter may be responsible for inverting the clock signal so as to generate an inverted clock signal that can be provided as input to the other core.

Paired processing unit architecture for improved microcontroller performance in multi-core processor

Methods and an apparatus for background subtraction are described. According to some implementations, the temporal history of a pixel location can be used to classify whether a current input pixel of a current input video frame is a background pixel or a foreground pixel. The classification can be made based on the number of matching pixels in corresponding pixel locations in background history planes. One of the background history planes can be updated according to the classified background pixels and persistent classified foreground pixels.

Methods and apparatus for video background subtraction

Techniques and systems are provided for processing video data. For example, techniques and systems are provided for performing content-adaptive blob filtering. A number of blobs generated for a video frame is determined. A size of a first blob from the blobs is determined, the first blob including pixels of at least a portion of a first foreground object in the video frame. The first blob is filtered from the plurality of blobs when the size of the first blob is less than a size threshold. The size threshold is determined based on the number of the plurality of blobs generated for the video frame.

Methods and systems of performing blob filtering in video analytics

In an example of this disclosure, a method may include receiving or generating image segmentation data for a plurality of pixels. The image segmentation data may include one or more image segmentation values for each pixel of the plurality of pixels. The method may include converting the one or more image segmentation values into one or more image component values. The method may include sending the one or more image component values corresponding to the one or more image segmentation values to a video encoder.

Compressing image segmentation data using video coding

The example techniques of this disclosure are directed to generating a stereoscopic view from an application designed to generate a mono view. For example, the techniques may modify source code of a vertex shader to cause the modified vertex shader, when executed, to generate graphics content for the images of the stereoscopic view. As another example, the techniques may modify a command that defines a viewport for the mono view to commands that define the viewports for the images of the stereoscopic view.

Stereoscopic conversion for shader based graphics content

The subject matter of this specification can be implemented in, among other things, a method of decoding video data that includes decoding compressed input video data using a first entropy coding technique to obtain first decoded data. The method further includes re-encoding the first decoded data using a second entropy coding technique that is different from the first entropy coding technique to obtain re-encoded data. The method further includes storing the re-encoded data in a storage device. The method further includes decoding the re-encoded data using the second entropy coding technique to obtain second decoded data.

Two-stage entropy decoding

This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.

Multi-stage tessellation for graphics rendering

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Cached memory system and cache controller for embedded digital signal processor

A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M&#xd7;N sub-screen tasks. Based on system profiling, M and N may be varied.

Quick pixel rendering processing

The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

Multi-media processor cache with cache line locking and unlocking

A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.

Automatic load balancing of a 3D graphics pipeline

A pilot searcher for CDMA and GPS signals. In one aspect, the searcher is operated in conjunction with a sample buffer in a 'real-time' or 'off-line' mode. The writing/reading of samples to/from the buffer may be performed in a TDM manner via a common port, and samples may be decimated and packed prior to storing in the buffer. In another aspect, the overall search for pilots is partitioned into a number of tasks, with each task corresponding to a search over a given sample segment and based on a particular set of parameter values. The tasks may be stored in a queue and performed one at a time based on their order in the queue. Prior to performing a new task, the parameter values for that task is downloaded to a set of configuration registers. The parameters may be ordered and linked such that only new values are downloaded.

Buffer-based GPS and CDMA pilot searcher

Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage units, and a data bus coupled to both storage units and the EMI unit. The two storage units are implemented external to the ASIC, and each storage unit is operable to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.

Growing community of inventors

San Diego, CA, United States of America

Jian Wei