Globespan Virata Corporation

Macom Technology Solutions Holdings, Inc.

Jian Wang

Wenwei Pan

Lujing Cai

Echere Iroaga

Marc R Delvaux

Naga Rajesh Doppalapudi

Nicolas Nodenot

Amaaduddin Zoab Quraishi

A system for calibration of a multi-channel transceiver includes a plurality of voltage regulator circuits, wherein each circuit is configured to produce a voltage for circuitry of one channel of a multi-channel transceiver. The system also includes an analog multiplexer circuit configured to selectively route the output of one of the plurality of voltage regulator circuits to a single comparison circuit. The single comparison circuit is configured to compare an output of one of the plurality of voltage regulator circuits to a target reference voltage and produce an error signal representing a difference between the output of one of the plurality of voltage regulators and the target reference voltage. The system further includes a processor configured to accept the error signal and produce a feedback signal for the one of the plurality of voltage regulator circuits. The feedback signal is operable to adjust the voltage to minimize the difference.

System and method for calibration of multi-channel transceivers

A method and apparatus for adapting an equalizer coefficients to a channel comprising filtering a high frequency error monitor slicer output and a data slicer output to isolate selected high frequency symbol values. Filtering a low frequency error monitor slicer output and the data slicer output to isolate selected low frequency symbol values. Generating a high frequency error monitor slicer threshold signal with a first adaptation module. Generating a low frequency error monitor slicer threshold signal with the first adaptation module or a second adaption module. Combining the high frequency error monitor slicer threshold signal and the low frequency error monitor slicer threshold signal to generate a difference signal. Integrating the difference signal with an accumulator to generate equalizer coefficients to adapt the equalizer to the channel. Providing the high frequency and low frequency error monitor slicer threshold signal to respective slicers.

Method and apparatus for CTLE equalizer adaptation based on samples from error slicers

A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses. In its broadest terms, the method can be described as: identifying a block data length, N, and an interleaver/de-interleaver depth, D; initializing a set of pointers associated with each of N memory segments; initializing a set of pointer maximum values responsive to the relative magnitude of N and D, identifying a memory index responsive to a base address and the set of pointer maximum values; using a memory segment identifier, a word identifier, and a byte identifier along with the memory index and the pointers to write/read the bytes of code words.

System and method for efficient convolutional interleaving/de-interleaving

A circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation is disclosed. The single modulo pointer of the present invention may be used to increase data throughput through a data interleaver/deinterleaver. A memory address pointer consistent with the present invention may be implemented with a multiplexer, an adder, a counter, and a modulo operator. A method for convolutional interleaving/deinterleaving is also disclosed.

Circuit and method for convolutional interleaving using a single modulo operation

A resource optimized interleaving/deinterleaving system comprising a Reed-Solomon encoder, a Reed-Solomon decoder, a state machine, and a memory is disclosed. Reed-Solomon encoded fastpath data is stored in memory. A stream of interleaved data with predefined parameters S, the number of DMT symbols per each Reed-Solomon codeword, D, the interleaving depth, and N, the block length is written into system memory at an adaptable rate determined by the Reed-Solomon encoder. The previously stored Reed-Solomon encoded fastpath data is automatically reassembled and buffered with the interleaved data to form appropriate DMT transmission symbols. The DMT transmission symbols are then read out of the system memory at a rate determined by the next processing function, i.e., tone ordering. A method of using one Reed-Solomon encoder/decoder with the integrated interleaving/deinterleaving system to support dual single latency DMT systems is also disclosed.

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Morganville, NJ, United States of America

Jian Wang