Huawei Technologies Co., Limited

Microsoft Technology Licensing, LLC

International Business Machines Corporation

Boe Technology Group Co., Ltd.

Beijing Boe Optoelectronics Technology Co., Ltd.

Future Wei Technologies, Inc.

Telefonaktiebolaget Lm Ericsson (publ)

Fujitsu Corporation

Chinese Academy of Sciences

Beijing Boe Display Technology Co., Ltd.

Beijing Xiaomi Mobile Software Co., Ltd.

Alibaba Group Holding Limited

Advanced New Technologies Co., Ltd.

Other

Symantec Corporation

Jian Wang

Haibo Xu

Da Wang

Zheng Chen

Qi Cheng Li

Qiang Wang

Nathan Edward Tenny

Lei Wang

Dongmei Zhang

Xin Zhou

Hao Chen

Bin Liu

Yue Li

Jing Li

Jie Ma

Hao Sun

Ning Liu

Zhenzhen Cao

Jun Yan

Wei Zhao

Hua Li

Jun Zhu

Feng Qu

Ralf Keller

Ying Liu

Fredrik Lindholm

Jianming Wu

Wei Liu

Bingzhao Li

Rong Li

Jun Wang

Hua Zhou

Zhi Hu Wang

Ning Duan

Ke Fei Wang

Gang Hua

Yang Liu

Qiang Wu

Chao Li

Lili Zhang

Qian Zhang

Jie Zhang

Tao Li

Yu Chen Zhou

Ke Zhang

Yalin Liu

Hongcheng Zhuang

Yuantao Zhang

Wen Tong

Peng Liu

Yi Wang

Li Wang

Bo Lin

Xin Li

Hui Jin

Hailin Xue

Bo Yang

Liang Xia

Jiantao Liu

Yunfei Qiao

Bin Xu

Gongzheng Zhang

David Nahamoo

Xiaolei Tie

Han Zhou

Huazi Zhang

Birgit Monika Pfitzmann

Yiqun Ge

Patrice Y Simard

Haisheng Wang

Lei Zhang

Yu Zhang

Hui Li

Xin Wang

Lei Guan

Dong Chen

Shipeng Li

Lixia Xue

Yan Cheng

Wenqing Zhao

Feng Wu

Xi Chen

Heung-Yeung Shum

Ningning Li

Haifeng Wang

Jian Li

Lingyun Shi

Jianguo Wang

Liang Zhang

Ming Zhou

Ming Jin Chen

Cheng Li

Qi Liu

Jing Yu

Xingqing Cheng

Junren Chang

Lei Liu

Wei Shan Dong

This disclosure provides an array substrate and a preparation method thereof as well as a touch display device. The array substrate includes: a substrate; a plurality of gate lines and a plurality of data lines located on the substrate, wherein the plurality of gate lines extend along a first direction and are arranged in a second direction different from the first direction, the plurality of data lines extend in the second direction and are arranged in the first direction, the plurality of gate lines intersect with the plurality of data lines to define a plurality of pixel areas; and a plurality of touch signal lines located on the substrate, wherein the plurality of touch signal lines extend in the second direction, each of the plurality of touch signal lines comprises a lower touch signal line and an upper touch signal line, and an edge of the upper touch signal line is spaced apart from an edge of the lower touch signal line in the first direction.

Array substrate and preparation method thereof as well as touch display device

An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

On-chip integrated circuit, data processing device, and data processing method

The present disclosure describes techniques for improved data processing. At least one management page may be generated by a host. The at least one management page comprises a plurality of management structures, and the at least one management page defines data instances, algorithms, and a computational environment. Computation may be initiated in a memory pool by performing a write operation of the at least one management page into the memory pool. The memory pool comprises a persistent memory and a plurality of field-programmable gate array (FPGA) cores. The computation in the memory pool comprises parallel data processing by at least a subset of the plurality of FPGA cores.

Data processing using a heterogeneous memory pool

An access method and apparatus, and a communication system is provided One example method includes: sending resource configuration information, where the resource configuration information configures a first time-frequency resource used for access of a plurality of terminals; and receiving access information from at least one of the plurality of terminals on the first time-frequency resource, where the access information of the terminal includes at least one of first identity information or status information of the terminal, the first identity information identifies the terminal, and the status information indicates a status of the terminal.

Access method and apparatus, and communication system

The disclosure relates to a data center, including: an IT equipment container provided with a server rack therein, an air-cooling equipment container, the IT equipment container having IT coolant inlet and outlet ports, and IT air inlet and outlet ports, the IT equipment container being prefabricated with a coolant inlet pipe connecting the IT coolant inlet port to a coolant inlet of a server rack, a coolant outlet pipe connecting the IT coolant outlet port to a coolant outlet of the server rack, and an air duct connecting the IT air outlet port to an air outlet of the server rack, and the IT air inlet port being in communication with interior of the IT equipment container; and having air-cooling air inlet and outlet ports, the air-cooling air inlet port and outlet ports being docked with the IT air outlet port and the IT air inlet port, respectively.

Container based data center with air cooling equipments

Techniques for improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor are provided. The techniques include obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and a number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and improving the computing efficiency of the processor by configuring the computational size of each computing core in the processor based on the k-th parameter.

Improving computing efficiency of a processor by optimizing a computational size of each computing core in the processor

Provided is a liquid crystal handwriting board. The liquid crystal handwriting board includes a first substrate, a second substrate, a third substrate, a first liquid crystal layer, and a second liquid crystal layer; wherein the first substrate includes: a first base, and a first pixel electrode and a transparent electrode, wherein the first pixel electrode is insulated from the transparent electrode, and the first pixel electrode is closer to the second substrate than the transparent electrode is; wherein the first substrate, the first liquid crystal layer and the second substrate are configured to form a display portion of the liquid crystal handwriting board; and the first substrate, the second liquid crystal layer and the third substrate are configured to form a writing portion of the liquid crystal handwriting board.

Liquid crystal handwriting board and manufacturing method therefor

A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

Storage circuit, chip, data processing method, and electronic device

The embodiments of the disclosure provide an immersion liquid cooling device and a liquid cooling system. The liquid cooling device includes a cabinet comprising a first cavity and a second cavity integrated on a side wall of the first cavity; and a heat exchange module adapted to be inserted into the second cavity via an opening on the second cavity, and comprising a heat exchanger, a coolant driving device and a guiding assembly, the heat exchanger being configured to cool the first coolant with the second coolant, the coolant driving device being configured to drive the first coolant to circulate between the second cavity and the first cavity, and the guiding assembly comprising a liquid flow channel configured to guide the first coolant from the coolant driving device to the heat exchanger.

Immersion liquid cooling device and liquid cooling system

A communication method includes that a first device deletes a first data packet. The first device sends first signaling to a second device, where the first signaling includes or indicates a first buffer, the first buffer is used to compress a second data packet or used to decompress a compressed second data packet, a serial number of the first data packet and a serial number of the second data packet are consecutive, the serial number of the second data packet follows the serial number of the first data packet, and the second device is a receiving device of the compressed second data packet.

Method and device to decompress data packets

The disclosure relates to a method and system for processing information in a content delivery network (CDN). The method includes: obtaining total bandwidth values at respective sampling time points within a management cycle, and arranging the total bandwidth values in chronological order; determining an interval between a first sampling time point and a second sampling time point as a management interval; determining usage ratios of respective bandwidth users according to a first bandwidth value used within the management interval by the bandwidth users sharing the CDN bandwidth, and a second bandwidth value in total used within the management interval by all of the bandwidth users sharing the CDN bandwidth; and managing, based on the usage ratios, bandwidth usage by the respective bandwidth users.

Method and system for processing information in CDN, device, and storage medium

The disclosure relates to a method, apparatus, electronic device and storage medium for scheduling for a content distribution network (CDN). The method includes: in response to an access request, received by an edge node, for a user to access a target website, determining whether target cache data corresponding to the target web site exists in the edge node; in response to absence of the target cache data in the edge node, reading address mapping data according to a load balancing strategy corresponding to the content delivery network; in response to determining that a target historical access network address corresponding to the target website exists in the address mapping data, determining a target edge address corresponding to the target historical access network address; and sending target cache data in the target edge address, corresponding to the target historical access network address to a user equipment through a cache service of the CDN.

Scheduling method and apparatus, storage medium and electronic device for content delivery network

A liquid crystal handwriting board is provided. The liquid crystal handwriting board includes a first substrate and a second substrate that are disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate; wherein the first substrate includes: a first base substrate, and a transistor and a pixel electrode disposed at a side, proximal to the second substrate, of the first base substrate, the transistor being electrically connected to the pixel electrode; wherein the transistor includes a channel region, wherein a ratio of an area of the channel region to an on-current of the transistor is greater than a ratio of an area of a channel region of a reference transistor to an on-current of the reference transistor.

Liquid crystal handwriting board

The disclosure provides a method and apparatus for configuring a network line, and a method for scheduling a network request. The method includes: obtaining a network line configuration request; displaying, in response to the network line configuration request, a network line configuration page, and obtaining first line configuration information based on the network line configuration page, where the first line configuration information includes first operator information and/or first geographic location information; querying a target priority corresponding to the first line configuration information; and writing line configuration information into a preset mapping table according to an order of the target priority from high to low, and transmitting the preset mapping table to a data plane, so as to make the network line corresponding to the line configuration information effective.

Method and apparatus for configuring network line, and method for scheduling network request

The application discloses example methods and apparatuses. One example method includes receiving, by a terminal, a power saving signal sent by a network device, wherein the power saving signal is used to indicate statuses of the terminal on N frequency resource units, and N is an integer greater than 1. The terminal then determines the statuses of the terminal on the N frequency resource units based on the power saving signal. By applying the technical solutions, the statuses of the terminal on the plurality of frequency resource units are indicated by using one power saving signal, without the need to correspondingly indicate the statuses of the terminal on the plurality of frequency resource units by using a plurality of power saving signals. This can reduce signaling overheads.

Terminal using network power saving signal to determine status on multiple frequency resource units

Growing community of inventors

Beijing, China

Jian Wang