Enpirion, Inc.

Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Jian Tan

Ashraf W Lotfi

Allen Frank Rozman

Wei Tang

Ashraf W Lofti

A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Laterally diffused metal oxide semiconductor device and method of forming the same

An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a switch formed on the semiconductor substrate and a driver switch of a driver configured to provide a drive signal to the switch and embodied in a transistor. The transistor includes a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Integrated circuit incorporating higher voltage devices and low voltage devices therein

A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region, and forming a doped region between the heavily doped region and the oppositely doped well. The doped region has a doping concentration profile less than a doping concentration profile of the heavily doped region. The method of forming the integrated circuit also includes forming a driver switch of a driver on the semiconductor substrate.

Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein

A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region. The method of forming the transistor still further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.

An integrated circuit formed on a semiconductor substrate and configured to accommodate higher voltage devices and low voltage devices therein. In one embodiment, the integrated circuit includes a transistor having a gate located over a channel region recessed into a semiconductor substrate, and a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor also includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region. The integrated circuit also includes a driver switch of a driver formed on the semiconductor substrate.

A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a power switch of a power train of the power converter on a semiconductor substrate, and forming a driver switch of a driver configured to provide a drive signal to the power switch and embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate, and forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well within the channel region, and forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.

Method of forming an integrated circuit employable with a power converter

An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a power switch of a power train of the power converter formed on a semiconductor substrate. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the power switch and embodied in a transistor including a gate located over a channel region recessed into the semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Integrated circuit employable with a power converter

A method of forming an integrated circuit employable with a power converter. In one embodiment, the method of forming the integrated circuit includes forming a transistor employable as a switch of a power train of the power converter by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, forming a heavily doped region adjacent the lightly doped region, and forming an oppositely doped well within the channel region. The method of forming the transistor further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well. The method of forming the integrated circuit also includes forming a driver switch of a driver to provide a drive signal to the transistor.

An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a transistor employable as a switch of a power train of the power converter including a gate located over a channel region recessed into a semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the transistor and formed on the semiconductor substrate.

Intergrated circuit employable with a power converter

A lateral metal-oxide semiconductor field effect transistor (MOSFET) formed over a substrate of a semiconductor wafer, a method of manufacturing the same and a semiconductor device incorporating the MOSFET or the method. In one embodiment, the MOSFET includes a silicon carbide layer located over or withing the substrate, a gate formed on the silicon carbide layer. The MOSFET further includes source and drain regions located in the silicon carbide layer and in contact with the gate, the silicon carbide layer increasing a breakdown voltage of the MOSFET.

SiC MOSFET for use as a power switch and a method of manufacturing the same

A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.

GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same

The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.

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Bridgewater, NJ, United States of America

Jian Tan