Macronix International Co., Ltd.

Jian-Syu Lin

Shang-Chi Yang

Su-Chueh Lo

Yi-Fan Chang

Jhen-Sheng Chih

Tung-Yu Li

A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

Continuous time linear equalizer of single-ended signal with input coupling capacitor

Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

Bond pad layout including floating conductive sections

Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing reference voltages, e.g., with current compensation, in memory systems, e.g., non-volatile memory systems. In one aspect, an integrated circuit includes: an operational amplifier configured to receive input voltages and a supply voltage and output a control voltage based on the input voltages and the supply voltage; an output circuitry configured to receive the control voltage from the operational amplifier and the supply voltage, provide the input voltages to the operational amplifier, and output a reference voltage; and a compensation circuitry coupled to the output circuitry and configured to output a compensation current to compensate the output circuitry such that the reference voltage is substantially constant. The output circuitry is configured to generate the reference voltage based on the control voltage and the compensation current.

Managing reference voltages in memory systems

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

Robust power-on-reset circuit with body effect technique

Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing startups of bandgap reference circuits in memory systems, e.g., non-volatile memory systems. In one aspect, an integrated circuit includes: a power supply switch configured to receive an original supply voltage and provide a controlled supply voltage controllable by an enabling signal, an operational amplifier configured to receive input voltages and the controlled supply voltage and output a gate control voltage, output circuitry configured to receive the gate control voltage and the controlled supply voltage, provide the input voltages to the operational amplifier, and output a reference voltage, and initialization circuitry coupled to the power supply switch, the operational amplifier, and the output circuitry and configured to initialize the controlled supply voltage and the gate control voltage to ground based on the enabling signal, such that the reference voltage increases from ground to a target voltage during a startup.

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Chiayi, Taiwan

Jian-Syu Lin