Elite Semiconductor Memory Technology, Inc

Jian-Sing Liou

Yu-Hsuan Cheng

Shu-Han Nien

Yi Heng Liu

A semiconductor memory device includes a memory bank of an open bit-line architecture and a word-line decoder. The memory bank is divided into a plurality of memory blocks in a bit-line direction, and each of the memory blocks includes a plurality of word lines, a plurality of bit lines and a plurality of memory cells which are grouped into a plurality of memory sections including two edge memory sections and at least one non-edge memory section. The word-line decoder generates a plurality of word-line enabling signals based on a plurality of address signals and activates one of the word lines for each of the two edge memory sections of one of the memory blocks and one of the word lines for one of the at least one non-edge memory section of each of the other memory blocks concurrently in an active mode according to the word-line enabling signals.

Semiconductor memory device and word-line activation method

A bandgap reference circuit incorporates first, second, and third current sources, first and second amplifiers, first and second bipolar transistors, a feedback device, a first resistor, and a second resistor. The first resistor is coupled between one input of the second amplifier and the base of the first bipolar transistor. The second resistor is coupled between the base of the first bipolar transistor and the base of the second bipolar transistor. The first and second amplifies and the first to third current sources constitute negative feedback loops which force the voltages at the inputs of the amplifiers to be substantially equal.

Bandgap reference circuit for providing a stable reference voltage at a lower voltage level

A method for determining a resistance calibration direction in ZQ calibration of a memory device includes: repeatedly comparing a reference voltage with an target voltage by a comparator to obtain an odd plurality of comparison outputs, each of the comparison outputs being one of a high-level state and a low-level state; determining a majority of the comparison outputs for their states by a ZQ calibration controller; and determining a resistance calibration direction according to the majority by the ZQ calibration controller so that the ZQ calibration controller generates a calibration code based on the resistance calibration direction and applies the calibration code to a resistance calibration unit to adjust the target voltage via the resistance calibration unit.

Method for determining resistance calibration direction in ZQ calibration of memory device

A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

Memory device capable of determining candidate wordline for refresh and control method thereof

A bandgap reference circuit incorporates first, second, and third current sources, first and second operational amplifiers, first and second bipolar transistors, a feedback device, a voltage divider, and a first resistor. The voltage divider divides a voltage difference between the third current source and the base of the second bipolar transistor to provide a reference voltage whose value is smaller than a silicon bandgap voltage.

Bandgap reference circuit

A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.

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Kaohsiung, Taiwan

Jian-Sing Liou