Realtek Semiconductor Inc.

Jian-Ru Lin

Chih-Cheng Lin

Shih-Hsiung Huang

Chien-Ming Wu

Liang-Huan Lei

Shih-Chieh Chen

Cheng-Pang Chan

Shin-Syong Huang

Chao-Cheng Lee

Yu-Chang Chen

Shih-Wei Wang

Che-Wei Chang

Wei-Chou Wang

Shih-Cheng Wang

Sung-Lin Tsai

Kuo-Wei Wu

Chia-Liang (Leon) Lin

Kai-Yin Liu

Chien-Sheng Chen

Cheng-Hsien Li

Rui Wang

Yung-Tai Chen

Shih-Hsiun Huang

Hung-Chen Chu

Hsiang-An Yang

Kuan-Chang Tsung

Chih-Jung Chiang

Shun-Te Tseng

Guan-Hong Ke

Tung-Hung Sung

A transmitter, a receiver and a transceiver are provided. The transceiver includes a hybrid transceiving circuit and a common-mode voltage control circuit. The hybrid transceiving circuit includes a digital-to-analog converter (DAC) circuit, a line driver coupled to the DAC circuit, a filtering and/or amplifying circuit coupled to the line driver, and an analog-to-digital converter (ADC) circuit coupled to the filtering and/or amplifying circuit. The common-mode voltage control circuit is electrically connected to a node of the hybrid transceiving circuit and is configured to detect a common-mode voltage of the node and to adjust the common-mode voltage of the node.

Transmitter, receiver and transceiver

Disclosed is a voltage-controlled oscillator (VCO) capable of providing an effective high VCO gain against slow change of an input voltage caused by the variation of manufacturing processes, temperature, voltage, etc. and providing an effective low VCO gain against rapid change of the input voltage for reducing jitter. The VCO includes: an input circuit generating an input current according to an input voltage; a first current supply circuit generating a first output current according to the input current; a second current supply circuit generating a second output current according to the input current; a filter coupled to the input circuit and the second current supply circuit and configured to slow down the influence caused by the variation of the input current on the second current supply circuit; and an oscillating circuit generating an output clock according to the first output current and the second output current.

Voltage-controlled oscillator and phase-locked loop

The present invention discloses an electrostatic discharge (ESD) protection circuit, including: a first terminal configured to receive a first voltage; a second terminal configured to receive a second voltage; a detection voltage generating circuit configured to provide a detection voltage according to the first voltage and the second voltage; a warning circuit configured to generate a control signal according to the detection voltage, in which the control signal indicates a normal condition when the detection voltage satisfies predetermined voltage setting, and the control signal indicates an abnormal condition when the detection voltage does not satisfy the predetermined voltage setting; and a protected circuit configured to carry out a self-protection operation when receiving the control signal indicating the abnormal condition.

Electrostatic discharge protection circuit

The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.

Calibration circuit and calibration method for ADC

A digital-to-analog converter (DAC) device includes a DAC circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to a plurality of least significant bits of an input signal. The second DAC circuit is configured to output a second signal according to a plurality of most significant bits of the input signal. A first turn-on time of at least one current source circuit in the first DAC circuit is configured to set the first signal.

Digital to analog converter device and current control method

A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.

Front-end receiving circuit and method for the same

A power supply device includes a power supply circuit, a detection circuit, and a control circuit. The power supply circuit is configured to output a supply voltage. The detection circuit is configured to sequentially provide a first predetermined resistance and a second predetermined resistance according to a plurality of switching signals, in order to operate with an electronic device and the supply voltage to sequentially obtain a first detection voltage and a second detection voltage. The control circuit is configured to generate the switching signals, and determine a load resistance of the electronic device according to the first detection voltage and the second detection voltage. The control circuit is further configured to determine whether the load resistance is within a predetermined resistance range, and the power supply circuit is further configured to drive the electronic device if the load resistance is within the predetermined resistance range.

Power supply device, detection circuit and power supply method thereof

A laser diode control circuit includes: a LD driver circuit for driving a laser diode; a direct current component remover circuit for generating a feedback signal based on a detected signal; a first conversion and filter circuit for generating a first filtered signal based on the feedback signal; a first rectifier for rectifying the first filtered signal to generate a first rectified signal; a reference signal generator for generating a reference signal; a second conversion and filter circuit for generating a second filtered signal based on the reference signal; a second rectifier for rectifying the second filtered signal to generate a second rectified signal; a rectified signals processing circuit for generating a processed signal based on the first and second rectified signals; and a comparator for generating a comparison signal based on the processed signal.

Laser diode control circuit with rectifier in feedback control loop

An impedance calibration device provided includes a timing device, a first transmitter, a first variable resistor, a second variable resistor and a first receiver. The first variable resistor is used to receive a first adjustment code. The second variable resistor is used to receive a second adjustment code. The first receiver generates a first contact digital signal according to a first contact voltage. The first receiver generates a first terminate digital signal according to a first terminate voltage and the first adjustment code. The first receiver generates a first load digital signal according to a load voltage and the second adjustment. The timing device dynamically adjust the first adjustment code and the second adjustment code according to the first contact digital signal, the first terminate digital signal and the first load digital signal.

Impedance calibration device and method thereof

A switch circuit comprising: a plurality of switches; a switching module; and a capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to a predetermined voltage, and the second terminal is coupled to a control terminal of at least the switch in a conductive mode via the switching module, to thereby control a conductive state for the at least one switch.

Switch circuit, sampling switch circuit and switch capacitor circuit

A pulse generation circuit, for outputting a pulse signal at an output terminal, comprises a PMOS, an NMOS and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled to a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate coupled to a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first logic signal, relating to the second gate control signal and a delay signal of the second gate control signal, and generates the second gate control signal according to the control signal and a second logic signal, relating to the first gate control signal and a delay signal of the first control signal.

DC voltage generation circuit and pulse generation circuit thereof

A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; an internal node; a first divider resistor positioned between the first signal node and the internal node; a second divider resistor positioned between the second signal node and the internal node; a comparing circuit for comparing a divided voltage at the internal node with a reference voltage to generate a comparison signal; and an adjusting circuit for adjusting resistance of at least one of the first and second adjustable resistors according to the comparison signal.

Transmission line driver circuit for adaptively calibrating impedance matching

The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.

Clock generator, communication device and sequential clock gating circuit

A pulse generation circuit for outputting a pulse signal at an output terminal, including: a PMOS, an NMOS, and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate that receives a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate that receives a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first delay signal and generates the second gate control signal according to the control signal and a second delay signal. The first delay signal is relevant to the second gate control signal and the control signal. The second delay signal is relevant to the first gate control signal and the control signal.

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Nantou County, Taiwan

Jian-Ru Lin