Qualcomm Incorporated

Advanced Micro Devices Corporation

Shenzhen Goodix Technology Co., Ltd.

Jian Mao

Raghu Sankuratri

Vineet Goel

Nariman Moezzi Madani

Skyler Jonathon Saleh

Bin Jiang

Maxim V Kazakov

Michael Drop

Youhong Lu

Ching-Hua Yeh

Hsinmin Wang

A method for detecting voice, an apparatus for detecting voice, and a chip for processing voice are disclosed. The apparatus includes: a sub-band generation module and a voice activity detection module; wherein the sub-band generation module is configured to process a current time-domain signal frame to obtain sub-band time-domain signals, and the voice activity detection module is configured to determine, according to amplitudes of the sub-band time-domain signals in the current time-domain signal frame, whether the current time-domain signal frame is an effective voice signal. The apparatus for detecting voice may be practiced in a time domain, such that complexity of algorithms is lowered, and power consumption is reduced.

Voice detection from sub-band time-domain signals

Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that 'skips stages.' An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.

Merged data path for triangle and box intersection test in ray tracing

An apparatus for canceling noise at an ear speaker includes a wideband active noise cancellation filter having a first bandwidth and configured to generate a wideband anti-noise signal from a received reference noise signal, a narrowband active noise cancellation filter having a second bandwidth smaller than the first bandwidth and configured to generate a narrowband anti-noise signal from an error noise signal, a filter between the ear speaker and an error microphone and configured to generate a feedback noise signal, and a controller. The controller is configured to eliminate the error noise signal by modifying coefficients of the wideband active noise cancellation filter and the narrowband active noise cancellation filter in response to the wideband anti-noise signal, the narrowband anti-noise signal, and the feedback noise signal.

Hybrid active noise control system

A processor sequences the application of submatrices at a matrix multiplier to reduce the number of input changes at an input register of the matrix multiplier. The matrix multiplier is configured to perform a matrix multiplication for a relatively small matrix. To multiply two larger matrices the GPU decomposes the larger matrices into smaller submatrices and stores the submatrices at input registers of the matrix multiplier in a sequence, thereby calculating each column of a result matrix. The GPU sequences the storage of the submatrices at the input registers to maintain input data at one of the input registers over multiple calculation cycles of the matrix multiplier thereby reducing power consumption at the GPU.

Matrix multiplier with submatrix sequencing

Systems and methods for a tessellation are described. The tessellation unit is configured to determine a number of points that reside along a first edge of a first ring within a domain, determine a first set of coordinates for a first portion of the points that reside along the first edge of the first ring within the domain, and determine a second set of coordinates for a second portion of the points that reside along the first edge of the first ring within the domain based on the first set of coordinates for the first portion. The tessellation unit is also configured to stitch points that reside along the first edge of the first ring with points that reside along a second edge of a second ring to divide the domain into a plurality of primitives that are mapped to a patch.

Computation reduced tessellation

Techniques described in the disclosure are generally related to generating points of a domain. A tessellation unit may determine outer ring point coordinates for a point of an outer ring of the domain, and inner ring point coordinates for a point of an inner ring of the domain. The inner ring is inner to the outer ring within the domain. The tessellation unit may enqueue the inner ring point coordinates at a location of a queue, read the inner ring point coordinates from the queue, and read the outer ring point coordinates from the queue when the outer ring is not an outermost ring, where the outer ring point coordinates were previously enqueued in the queue when the outer ring was a previous inner ring. The tessellation unit may connect the inner ring coordinates and the outer ring coordinates each of which being read from the queue.

Storage structures for stitching primitives in graphics processing

Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals

A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

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San Diego, CA, United States of America

Jian Mao