Cadence Design Systems, Inc.

Sigrity, Inc.

Jian Liu

An-Yu Kuo

Jiayuan Fang

Jian Feng Chen

Xiande Cao

Xiao Lin

Jilin Tan

Chun-Teh Kao

Jing Wang

Tiejun Yu

Yanrui Wu

Mazen Issam Baida

Anyu Kuo

Karthikeyan Mahadevan

Mingjin Zhang

Kaiyu Mao

Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify connectivity of an electronic design that includes an embedded circuit, and the embedded circuit is located between a first actual layer and a second actual layer of the electronic design. The electronic design is then transformed, but one or more embedded circuit modules, into a transformed electronic design at least by generating one or more artificial interconnects between the embedded circuit and a plurality of metal patches. The connectivity may be re-established based at least in part upon the plurality of metal patches. The electronic design may then be implemented based at least in part upon predicted behaviors of the transformed electronic design.

Methods, systems, and computer program product for implementing an electronic design having embedded circuits

Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

Methods, systems, and computer program product for implementing an electronic design with optimization maps

Disclosed are techniques for implementing physics aware model reduction for a design. These techniques identify a design model and generate a first set of solutions with a first discretization scheme and a plurality of inputs. A second discretization scheme may be generated at least by performing geometry simplification and re-discretization based in part or in whole on one or more distributions from the first set of solution. With the second discretization scheme, a second set of solutions may be generated with the second discretization scheme and the plurality of inputs.

Methods, systems, and computer program product for implementing physics aware model reduction for three-dimensional designs

The present disclosure relates to a system and method for modeling an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design. Embodiments may also include partitioning, at a graphical user interface configured to display at least a portion of the electronic circuit design, at least one portion of the electronic circuit design into one or more sub-zones and generating, at the graphical user interface, one or more ports at each interface between one or more sub-zones. Embodiments may further include receiving a selection for an electromagnetic (EM) solver for each of the one or more sub-zones. Embodiments may also include modeling each of the one or more sub-zones.

System and method for modeling electronic circuit designs

Disclosed are techniques for implementing coplanar waveguide transmission lines in an electronic design. These techniques identify one or more electrically conductive shapes and a plurality of edge segments thereof in an electronic design. A plurality of model trace segments may be constructed based in part or in whole upon a plurality of edge segments. One or more coupled line groups may be generated with the plurality of model trace segments and one or more actual trace segments for a model of the electronic design. Electrical analyses or simulations may be performed on the model to generate electrical analysis results. The electronic design may then be devised or revised based on extracted parameter values of the electrical analysis results.

Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs

Disclosed are techniques for devising an electronic design with disconnected field domains. These techniques identify a plurality of electrically conductive shapes of an electronic design, add a plurality of patches to a model of the electronic design for multiple apertures in the electronic design, analyze the model to generate analysis results for the electronic design, and devise or implement the electronic design based in part or in whole upon the analysis, wherein an aperture of the multiple apertures causes disconnected electromagnetic field domains in the model.

Methods, systems, and articles of manufacture for implementing an electronic design with disconnected field domains

Disclosed are techniques for model-based electronic design implementation with a hybrid solver. These techniques generate an extruded via from a linkage node to a reference metal plane that is added to an analysis model for at least a portion of an electronic design. The analysis model for the at least the portion is generated at least by re-establishing interconnection between the at least the portion and a linkage circuit element with the extruded via. At least the portion of the electronic design may further be implemented using the analysis or simulation results that are generated by using the hybrid solver on the model, without using three-dimensional solvers, for a three-dimensional model of the electronic design.

Methods, systems, and articles of manufacture for implementing electronic designs with a pseudo-3D analysis mechanism

Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.

Methods, systems, and computer-readable media for model order reduction in electromagnetic simulation and modeling

Methods, systems, and computer-readable media for simulating an electronic packaging structure are disclosed. The methods include providing an electromagnetic simulation framework for simulating the electronic packaging structure that includes at least two planes and an interconnect transitional component. The framework includes solvers for simulation based on parallel-plate, strip line, and microstrip line modes. The method also includes defining ports of the component based on modes, computing a network function characterizing the properties of the component; and associating ports with solvers of the framework.

Methods, systems, and computer-readable media for simulating interconnects in electronic packaging structures

Method, system, and computer readable medium are disclosed for analyzing electrical properties of a circuit. The method may comprise: providing a network model including at least one network parameter, the network parameter being defined over a frequency range; converting the network parameter into an intermediate network parameter having first and second portions; identifying first and second frequencies defining a frequency sub-range; replacing the first portion of the intermediate network parameter with a DC value when a frequency associated with the intermediate network parameter is lower than the first frequency; replacing the first portion of the intermediate network parameter with a transitional value when the frequency associated with the intermediate network parameter is within the frequency sub-range; and converting the intermediate network parameter with the replaced first portion into an updated network parameter.

Growing community of inventors

Dublin, CA, United States of America

Jian Liu