Qualcomm Incorporated

Other

University of California

Jian Lin

Gilbert Christopher Sih

Simon Turner

Nischal Abrol

Sanjay K Jha

Li Feng Zhang

Inyup Kang

Daniel Fred Filipovic

Hanfang Pan

Haitao Zhang

Shanshan Wang

Emilija Milorad Simic

Qiuzhen Zou

Insung Kang

Saed G Younis

Thomas Wilborn

Cengiz S Ozkan

Mihrimah Ozkan

Way-Shing Lee

Deepu John

Nicholas K Yu

Ralph E Kaufman

Quaeed Motiwala

Scott Howard King

Charles E Sakamaki

Prashant A Kantak

Shirui Guo

Ali B Guvenc

Rajat K Paul

Maziar Ghazinejad

Miro Penchev

Kerry Taylor

Jiebin Zhong

Quizhen Zou

Methods of fabricating a graphene film are disclosed. An example method can include providing a substrate, heating the substrate between about 600&#xb0; C. and about 1100&#xb0; C. in a chamber, and introducing a carbon source into the chamber at a temperature between about 600&#xb0; C. and about 1100&#xb0; C. for about 10 seconds to about 1 minute. The method can further include cooling the substrate to about room temperature to form the graphene film Methods of fabricating pillared graphene nano structures and graphene based devices are also provided.

Methods of fabricating pillared graphene nanostructures

Systems, methods and apparatus for wireless communication are provided. In one aspect, the method comprises receiving at least one downlink packet. The method further comprises generating an acknowledge message in response to receiving the at least one downlink packet. The method further comprises prioritizing the acknowledge message in a buffer according to a probability, the probability based at least in part on a current utilization level of the buffer. The method may further comprise one or more of the following: setting the probability to a first value when the utilization level is below a first level, setting the probability to a second value when the utilization level is above the first level and below a second level, and setting the probability to a third value when the utilization level is above the second level. The second value may be adjusted based on feedback corresponding to a downlink throughput.

Systems, methods and apparatus for adaptive persistent acknowledge priority control for bi-directional TCP throughput optimization

An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, 'un-escaping' the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

HDLC hardware accelerator

A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length

Wireless mobile communication device includes unified memory portion; processing units coupled with, and communicating through, unified memory; fault inhibitor coupled with unified memory inhibiting operational fault from nocent informon. Memory, fault inhibitor, and processing units fabricated on monolithic integrated circuit as system-on-chip disposed in wireless mobile personal host. Multiprocessor module includes fault inhibitor and applications and communications processing units and buses, coupled with unified memory. Integrated functional constituent can include coprocessor, accelerator, operational control unit, interprocessor controller, memory controller, bus management unit, bridge, arbiters, and transceiver. Method inhibits operational fault from nocent informon, setting device in operational or fallback state.

Wireless multiprocessor system-on-chip with unified memory and fault inhibitor

A method and system for transferring data bytes includes a first memory adapted to store a plurality of multiple-byte data words including header field bytes and one or more data field bytes. The system also includes a second memory adapted to store data field bytes transferred thereto from the first memory. A controller coupled to the first and second memories reads a data word including the header field byte and the one or more data field bytes out of the first memory. The system also includes a data packer coupled to the controller and the second memory. The controller and data packer cooperate to transfer the one or more data field bytes of the first data word read from the first memory to the second memory. The data packer stores only the one or more data field bytes in the second memory contiguously with a previously transferred and stored data field byte.

Method and system for efficient transfer of data between custom application specific integrated circuit hardware and an embedded microprocessor

A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories. An instruction decoder decodes the instructions from the instruction memory and generates control signals that cause data to be exchanged between the various registers, data memories, and functional units, allowing multiple operations to be performed during each clock cycle.

Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control

A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory is separate from the set of three data memories.

Digital signal processor having multiple access registers

The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.

Low power latch requiring reduced circuit area

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San Diego, CA, United States of America

Jian Lin