Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Nec Corporation

Zenith Data Systems Corporation

Packard Bell Nec

Bull Nh Information Systems, Inc.

Jian-Kuo Shen

Ming T Miu

Thomas F Joyce

John J Bradley

Richard P Kelly

Robert C Miller

Chester M Nibby, Jr

Theodore R Staplin, Jr

Bruno DiPlacido, Jr

Jeffrey S Somers

Thomas L Murray, Jr

James F Bertone

Michelle A Pence

G Lewis Steiner

Marc Sanfacon

Martin Massucci

Lance J McNally

Robert V Ledoux

Richard L King

Deborah K Staplin

William S Wu

Suresh K Marisetty

Norman J Rasmussen

David E Cushing

Puthiya K Nizar

William Panepinto, Jr

Forrest M Phillips

Ming-Tzer Miu

Richard A Lemay

George J Barlow

Thomas O Holtey

James W Keeley

Michel M Raguin

Boyd E Darden

Lance T McNally

Romeo Kharileh

Robert V Ledoux, Deceased

Lewis G Steiner

Bruno Diplacido

Lance Mcnally

The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Symmetric multiprocessing system with unified environment and distributed system functions

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Symmetric multiprocessing system with unified environment and

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Adaptively generating timing signals for access to various memory

The decoding of certain instructions cause an instruction unit of a production line data processing system to stall. Instructions still in the production line are executed, but no new instructions are sent into the production line until the instruction that caused the stall condition is executed. The execution of the instruction that caused the stall is completed by an execution unit taking over control of an address unit.

Control store addressing from multiple sources

The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

Recovery method and apparatus for a pipelined processing unit of a

A pipelined processing unit which includes an instruction unit stage containing logic management apparatus for processing a set of complex instructions. The logic management apparatus includes state control circuits which produce a series or sequence of control states used in tracking the different types of instructions of the complex instruction set being processed. Different ones of the states are used for different types of instructions so as to enable the different pipeline stages to operate both independently and jointly to complete the execution of different instructions of the complex instruction set.

State controlled instruction logic management apparatus included in a

In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

Method for reexecuting instruction by altering high bits of instruction

A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource registers corresponding in number to the number of instructions which can be processed concurrently by the processing unit. Decode circuits in response to each new instruction received by the instruction unit generate one or more sets of bit indication signals designating those resources required by the specific pipeline stage(s) executing the instruction for completing the execution of the instruction which are shared by those stages capable of completing the execution of instructions. Comparison circuits compare the set of bit indication signals for each new instruction that corresponds to resources needed by an earlier pipeline stage which in the preferred embodiment corresponds to a secondary execution unit, with the stored sets of bit indication signals for determining the presence of any resource conflict.

Resource conflict detection method and apparatus included in a pipelined

A separate register file memory is included in at least two units of a pipelined processor which are located on separate integrated circuit chips. The register file memories of the units are interconnected so as to share certain input data register stages to enable updating to take place within a minimum of time. Each unit has a microprogrammed control unit which automatically provides update commands during the unit's cycles of operation. The signals from each microprogrammed control unit are applied to both register file memories enabling both memories to be updated during successive cycles of operation and thereby function collectively as one unit. This ensures that both units have access to the same most recently updated user visible information enabling both units to complete the execution of different instructions entering pipeline.

Mechanism for automatically updating multiple unit register file

A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.

Multiprocessors on a single semiconductor chip

A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations. By writing data into the input registers instead of the register file memory in a previous cycle, the time required for writing is reduced to a minimum.

Dual read/write register file memory

A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Means for transferring firmware signals between a control store and a

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Belmont, MA, United States of America

Jian-Kuo Shen