Maxlinear, Inc.

Marvell Asia Pte., Ltd.

Jian-Hung Lin

Shaoan Dai

Xing Wu

Junyi Xu

Yuansheng Jin

Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.

Interference mitigation in high speed ethernet communication networks

Systems and methods are provided for enhanced parallel bit-interleaving. The parallel bit-interleaving may include, in each of a plurality of cycles, reading a number of bits from an input bitstream; processing the read bits, with the processing including applying a first adjustment to a first combination of bits that includes the read bits and additional bits, wherein each of the additional bits includes a previously read bit in the input bitstream or a pre-set bit; when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that includes bits corresponding to previously read bits, wherein the conditional criteria include completing processing of a full column; writing into memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and reading from the memory a number of bits, for generating an output corresponding to the particular cycle.

Methods and systems for parallel column twist interleaving

Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

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Laguna Niguel, CA, United States of America

Jian-Hung Lin