Micron Technology Incorporated

Jian Huang

Zhenming Zhou

Murong Lang

Jiangli Zhu

Zhongguang Xu

Tingjun Xie

Nagendra Prasad Ganesh Rao

Sead Zildzic, Jr

Zhenlei Shen

Sead Zildzic

Paing Z Htet

Thomas Fiala

A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.

Managing an adaptive data path selection threshold for a memory sub-system

A system can include a memory device containing blocks made up of wordlines respectively connected to sets of memory cells, and a processing device, operatively coupled with the memory device to perform operations including responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block. The operations can also include responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric, and performing, using the read voltage offset, a read operation responsive to the read request.

Read level compensation for partially programmed blocks of memory devices

A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

Adaptive frequency control for high-speed memory devices

A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

Managing the programming of an open translation unit

A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.

Managing a hybrid error recovery process in a memory sub-system

A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

Open translation unit management using an adaptive read threshold

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.

Performing data integrity checks to identify defective wordlines

An error associated with a read operation corresponding to a memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.

Decreasing a quantity of queues to adjust a read throughput level for a data recovery operation

A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

Recovery management of retired super management units

A programming operation is performed on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells are comprised by an open translation unit (TU) of memory cells. It is determined that a second set of memory cells comprised by the open TU are in a coarse programming state, wherein the second set of memory cells is addressable by a second WL. In response to determining that the second set of memory cells satisfies a threshold criterion, a programming state verify level associated with the second WL is reduced by a verify level offset. A programming state gate step size associated with each WL of the open TU is reduced by a predefined value. A programming operation is performed on the second set of memory cells using the reduced programming state verify level and the reduced programming state gate step size.

A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.

A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, selecting, by the processing device, a first partition located on a first die of the memory device. The operations performed by the processing device further include selecting, based on a predefined partition offset reflecting a physical layout of the memory device, a second partition located on a second die of the memory device. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Generating codewords with diverse physical addresses for 3DXP memory devices

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Codeword error leveling for 3DXP memory devices

An error associated with a read operation corresponding to a target memory die of a memory sub-system is detected. In response to detecting the error, a first read throughput level of the memory sub-system is identified. The first read throughput level is adjusted to a second read throughput level. A read retry operation associated with the target memory die is executed at the second read throughput level.

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Union City, CA, United States of America

Jian Huang