Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Zte (usa) Inc.

East China University of Science and Technology

Amlogic (shanghai) Co., Ltd.

Grace Semiconductor Manufacturing Corporation

Zte Corporation

Jian Hu

Weiran Kong

Jing Gu

Bo Zhang

Guangjun Yang

Wenfeng Zhang

Bin Yu

Zhong Xian Li

Zhongda Du

Zhifeng Ma

Bo Yang

Jun Xiao

Hong Jiang

Binghan Li

Guobin Ren

Xiaoyong Xu

Minghui Qi

Yuhong Duan

Chengyu Gong

Xingyu Chen

Chaoyang Luo

Xuhua Zhang

The PWM waveform generation device comprises a time-division multiplexing module, wherein the time-division multiplexing module is configured for receiving a first preprocessing signal and a second preprocessing signal output by two system clock sources, performing a first time-division processing on the first preprocessing signal to obtain a first time-division signal, and performing a second time-division processing on the second preprocessing signal to obtain a second time-division signal according to a preset strategy, performing multiplexing processing on the first time-division signal and the second time-division signal to obtain a PWM output signal, wherein an output frequency of the PWM output signal is a default standard clock frequency. The present invention has the advantages that the cycle length of one cycle of a PWM waveform depends on cycles of two preprocessing waveforms and the number of the cycles, such that the output waveform frequency may be calibrated to a desired frequency.

PWM waveform generation device and method thereof

A tebuconazole polymorph and a preparation method therefor are described. In particular, a polymorph of (RS)-1-(4-chloropheny)-4,4-dimethyl-3-(1H-1,2,4-triazol-1-ylmethyl) pentan-3-ol, a preparation method therefor and use thereof are provided. The tebuconazole polymorph has a high purity and excellent crystallization properties, is stable under high humidity, high temperature and light conditions, has excellent solubility, and has high processing properties for formulations, high biological activities and good sterilization effects. The preparation method is simple, has stable processes, and can be implemented on a large scale. The polymorph can greatly improve the quality control and industrial application of tebuconazole-containing pesticides.

Tebuconazole polymorph and preparation method therefor

Semiconductor structures are provided. An exemplary semiconductor structure includes a semiconductor substrate having a first region and a second region and a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region. A first oxide layer is on side surfaces of the plurality of first fins; and a second oxide layer is on side surfaces of the second fins. A corner between a top surface and a side surface of each first fin is a first rounded corner. A corner between a top surface and a side surface of each second fin is a second rounded corner. A radius of curvature of the first rounded corner is different from a radius of curvature of the second corner.

Semiconductor structure

An EEPROM and methods for erasing, programming and reading it, the EEPROM includes a plurality of split-gate storage arrays, each of the plurality of split-gate storage cells including a source connected with a first bit line, a drain connected with a second bit line, a first control gate connected with a first store position, a word line gate connected with a word line and a second control gate connected with a second store position; and the first control gate is connected with a first control gate line, and the second control gate is connected with a second control gate line, wherein every N columns of the split-gate storage cells are formed on a first well structure, adjacent first well structures are separated by a second well structures having a different doping type with that of the first well structures, and N is a positive integer.

EEPROM, and methods for erasing, programming and reading the EEPROM

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication process includes providing a semiconductor substrate having a first region and a second region and having a plurality of first fins in the first region and a plurality of second fins in the second region; performing a first oxidation process on the first fins to form a first oxide layer on surfaces of the first fins and to cause corners between top surfaces and side surface of the first fins to form first rounded corners; and performing a second oxidation process on the second fins to form a second oxide layer on surfaces of the second fins and to cause corners between top surfaces and side surface of the second fins to form second rounded corners. A radius of curvature of the first rounded corner is different from a radius of curvature of the second rounded corner.

Semiconductor structure and fabrication method thereof

A memory array and a method for reading, programming and erasing the same are provided. The memory array includes flash memory cells arranged in an array, each flash memory cell includes a first and a second split-gate flash memory cell; a first control gate of the first split-gate flash memory cell is connected with a first control gate of the second split-gate flash memory cell and a first control gate line, a second control gate of the first split-gate flash memory cell is connected with a second control gate of the second split-gate flash memory cell and a second control gate line; a word line gate of the first split-gate flash memory cell is connected with a word line gate of the second split-gate flash memory cell and a word line; two drains of the first and second split-gate flash memory cells share a same bit line.

Memory array and method for reading, programming and erasing the same

A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.

Flash memory unit and memory array, and programming, erasing and reading method thereof

Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced.

Charge pump system and memory

A SRAM cell and a forming method thereof are provided. The SRAM cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor. The method includes: providing a semiconductor substrate; forming a pull-up transistor, a pull-down transistor and a pass gate transistor on the semiconductor substrate; forming a tensile stress film covering the pull-up and pull-down transistors; and forming an interlayer dielectric isolating layer covering the tensile stress film and the pass gate transistor. Write margin of the SRAM cell may be increased and an area of the SRAM cell may be reduced.

Static random access memory cell and forming method thereof

A method and system for dynamic adjustment of downlink/uplink resource allocation ratio in a long-term evolution (LTE) time division duplex (TDD) system is disclosed. The method includes replacing at least one uplink subframe in a subframe pattern with at least one of a mute subframe and a mute uplink pilot timeslot (UpPTS), within a geographical guard area that isolates at least two areas having different TDD allocation patterns. The method further includes scheduling an uplink transmission from at least one mobile terminal such that the at least one of the mute subframe and the mute UpPTS are unused. A simple solution or a TDD configuration index substitution solution, or any combination thereof, may be used to control the uplink transmission involving a mute subframe or a mute UpPTS.

Method and system for dynamic adjustment of downlink/uplink allocation ratio in LTE/TDD system

A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.

Growing community of inventors

Shanghai, China

Jian Hu