Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Richtek Technology Corporation

Richtek Technology Corporation, R.o.c

Jian-Hsing Lee

Jiaw-Ren Shih

Shui-Hung Chen

Yi-Hsun Wu

Kuo-Reay Peng

Shao-Chang Huang

Hwa-Chyi Chiou

Hung-Der Su

Yu-Chang Jong

Chih-Hsuan Lin

Ming-Chou Ho

Ming-Song Sheu

Jing-Meng Liu

Yeh-Jen Huang

Kuo-Feng Yu

Kuo-Chio Liu

Wen-Hsin Lin

Yeh-Ning Jou

Yi-Hsu Wu

Chun-Chien Tsai

Di-Son Kuo

Juang-Ke Yeh

Tao Cheng

Chun-Jung Chiu

Juang-Ker Yeh

Ta-Lee Yu

Karuna Nidhi

Yu-Kai Wang

Tzu-Cheng Kao

Chang-Min Lin

Jian-Ren Shih

Deng-Shun Chang

Ruey-Hsin Liu

Kuo-Ming Wu

Yai-Fen Lin

Chrong Jung Lin

Lin-June Wu

Chieh-Yao Chuang

Huan-Ping Chu

Hsien-Feng Liao

Anthony Oates

Jyh-Min Jiang

Shiou-Hann Liaw

Boon-Khim Liew

Fu Chin Yang

Ting-Yu Chang

Jin-Lian Su

Huey-Liang Hwang

Li-Yang Hong

Jung-Ke Yeh

Shui-Hun Chen

Shih-Chyi Wong

Hsiu-Han Liao

Shui-Hunyi Chen

Ping-Lung Liao

Yao-Wu Feng

Bing-Lung Liao

Dun-Nian Yaung

Feng-Chi Hung

Tsung-Yi Huang

Shin-Cheng Lin

Ming-Hsiang Song

Hsien-Chin Lin

Yu-Hao Ho

Tong-Chern Ong

Yi-Chun Lin

Juing-Yi Wu

Ching-Yi Hsu

Hung-Lin Chen

Chi-Chih Chen

Yu-Chen Wu

Pao-Kang Niu

Shu-Chuan Lee

Kuan-Lun Chang

Mau-Lin Wu

Chuan-Ying Lee

Ko-Yi Lee

King-Ho Ping

Chau-Neng Wu

Chi-San Wei

Hung Der Su

Chong-Gim Gan

Nai-Lun Cheng

Chia-Hung Tunga

Tiaw-Ren Shih

Jiaw Ren Shih

Shui-Hung Shen

Kuo Reay Peng

Jiaw-Ren Shin

Shui Hun Yi Chen

D J Perng

Cs Tang

Huang Yung-Sheng

Dah-Jyh Perng

Yung-Tien Tsai

Chin-Hsin Tang

Chung-Yu Hung

A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.

Semiconductor structure with a gate and a shielding structure

A semiconductor device includes a gate electrode disposed on a substrate. A source region and a drain region are disposed in the substrate and located on two sides of the gate electrode respectively. The drain region includes a plurality of drain segments that are laterally separated from each other. These drain segments have a first conductive type and the substrate has a second conductive type. A plurality of drain contacts is electrically connected to the drain segments. Each drain segment corresponds to at least one of these drain contacts. A drain electrode is electrically connected to these drain contacts. A source electrode is electrically connected to the source region.

Semiconductor device

An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.

Electrostatic discharge protection device

An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.

Electrostatic discharge protection structure

A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.

Protection circuit

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Semiconductor device structure comprising source and drain protective circuits against electrostatic discharge (ESD)

An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.

Electronic device and electrostatic discharge protection circuit

A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.

Control circuit and high electron mobility element

A semiconductor device including a substrate, a seed layer, a buffer layer, a channel layer, a barrier layer, a gate structure, a first source/drain structure, a second source/drain structure, and a contact is provided. The seed layer is disposed on the substrate. The buffer layer is disposed on the seed layer. The channel layer is disposed on the buffer layer. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The first and second source/drain structures are disposed on opposite sides of the gate structure. The contact contacts the first source/drain structure. The distance between the gate structure and the contact is between 0.5 micrometers and 30 micrometers.

Semiconductor device and operation circuit

An electrostatic discharge protection device including a substrate, a first PNP element, a second PNP element, and an isolation region is provided. The substrate has a P-type conductivity. The first and second PNP elements are formed in the substrate. The isolation region isolates the first and second PNP elements.

A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

Integrated circuits using guard rings for ESD systems

A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Methods for forming integrated circuit having guard rings

An electrostatic discharge protection (ESD) circuit is provided for a semiconductor element. The semiconductor element includes first and second drain/source electrodes and is surrounded by a deep well region. The ESD circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal and includes a first control terminal electrically connected to the deep well region and generates a first control signal. The first discharge circuit is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to potential states of the deep well region and the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

Electrostatic discharge protection circuits and semiconductor circuits

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.

Semiconductor device structures

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Hsin-Chu, Taiwan

Jian-Hsing Lee