Taiwan Semiconductor Manufacturing Comp. Ltd.

Jian-Hong Lin

Yung-Huei Lee

Hsin-Chun Chang

Ming-Yih Wang

Tzu-Li Lee

Ming-Hong Hsieh

Chwei-Ching Chiu

Chien-Jung Wang

Yinlung Lu

Chun-Wei Chang

Chin-Shan Wang

Bi-Ling Lin

Hsien-Wei Chen

Yu-Ching Lee

Kang-Cheng Lin

Yu-Lun Chueh

Chiung-Ting Ou

Kuo-Yen Liu

Pei-Chun Liao

Tsung-Cheng Chan

Chien-Neng Liao

Chun-Lung Huang

Yih-Ching Wang

Jiaw-Ren Shih

Jun He

Shun-Yi Lee

Mingni Chang

Wei-Cheng Liu

Hsuan-Ming Huang

Shiou-Fan Chen

Chih-Hung Nien

Chien Shih Tsai

Lee-Der Chen

Chin Chuan Peng

Chun-wei Chang

Wen-Hsien Kuo

Shin-Puu Jeng

Hao-Yi Tsai

Chih-Wei Lin

Hsueh-Chung Chen

Shu-Yuan Ku

Hui Yu Lee

Ming-Hsien Lin

Shih-Hsun Hsu

Jye-Yen Cheng

Yi-Lung Cheng

Yung-Sheng Huang

Te-Liang Lee

Dawei Heh

Wenhsien Kuo

Ying-Jen Kao

Shou-Chung Lee

Yu Ching Lee

Jyh-Weei Hsia

Bor-Jou Wei

Chih-Tao Lin

Shu-yuan Ku

A package component includes a first substrate and a first conductive layer. The first substrate has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed over the first surface of the first substrate. The first conductive layer includes a first conductive feature and a second conductive feature over the first conductive feature. The second conductive features covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the second conductive feature. The first substrate includes a single-sided or a double-sided copper-clad laminate.

Package component

A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Phase-change memory cell and method for fabricating the same

An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Through-circuit Vias in interconnect structures

Through-circuit vias in interconnect structures

A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Semiconductor arrangement and method of forming

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Semiconductor structure and method of manufacturing the same

Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.

System and method for extending lifetime of memory device

A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.

One-time programmable memory device including anti-fuse element

An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Interconnect structure and forming method thereof

A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Package component and forming method thereof

A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.

One-time programmable memory device including anti-fuse element and manufacturing method thereof

A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

Method of fabricating semiconductor device including dummy via anchored to dummy metal layer

Growing community of inventors

Yunlin, Taiwan

Jian-Hong Lin